1514 lines
60 KiB
C++
1514 lines
60 KiB
C++
/*
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* Xhci.cpp
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* xHCI (USB 3.x) Host Controller driver
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* Copyright (c) 2025 Daniel Hammer
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*/
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#include "Xhci.hpp"
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#include "UsbDevice.hpp"
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#include "HidKeyboard.hpp"
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#include "HidMouse.hpp"
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#include "MassStorage.hpp"
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#include <Pci/Pci.hpp>
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#include <Terminal/Terminal.hpp>
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#include <CppLib/Stream.hpp>
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#include <Memory/HHDM.hpp>
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#include <Memory/Paging.hpp>
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#include <Memory/PageFrameAllocator.hpp>
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#include <Libraries/Memory.hpp>
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#include <Hal/Apic/Interrupts.hpp>
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#include <Timekeeping/ApicTimer.hpp>
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#include <atomic>
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using namespace Kt;
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static void BusyWaitMs(uint64_t ms) {
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uint64_t flags;
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asm volatile("pushfq; pop %0" : "=r"(flags));
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if (flags & (1 << 9)) {
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// Interrupts enabled — use timer-based delay
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uint64_t start = Timekeeping::GetMilliseconds();
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while (Timekeeping::GetMilliseconds() - start < ms) {
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asm volatile("pause" ::: "memory");
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}
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} else {
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// Interrupts disabled (e.g. timer tick context) — use I/O port delay
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// Each outb to port 0x80 takes ~1µs on x86
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for (uint64_t i = 0; i < ms * 1000; i++) {
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asm volatile("outb %%al, $0x80" ::: "memory");
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}
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}
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}
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namespace Drivers::USB::Xhci {
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// -------------------------------------------------------------------------
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// Static state
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// -------------------------------------------------------------------------
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static bool g_initialized = false;
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static bool g_bootScanComplete = false; // true after initial port scan finishes
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// Hot-plug deferred work
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static volatile bool g_hotplugPending[MAX_PORTS] = {};
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static volatile bool g_deferredWorkPending = false;
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static std::atomic<bool> g_hotplugProcessing{false};
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// MMIO region pointers
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static volatile uint8_t* g_mmioBase = nullptr;
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static uint8_t g_capLength = 0;
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static volatile uint8_t* g_opBase = nullptr;
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static volatile uint8_t* g_rtBase = nullptr;
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static volatile uint8_t* g_dbBase = nullptr;
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// Controller parameters
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static uint32_t g_maxSlots = 0;
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static uint32_t g_maxPorts = 0;
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// DCBAA (Device Context Base Address Array) -- not static: accessed by UsbDevice.cpp
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uint64_t* g_dcbaa = nullptr;
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static uint64_t g_dcbaaPhys = 0;
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// Command ring
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static TRB* g_cmdRing = nullptr;
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static uint64_t g_cmdRingPhys = 0;
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static uint32_t g_cmdRingEnqueue = 0;
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static bool g_cmdRingCCS = true;
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// Event ring
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static TRB* g_evtRing = nullptr;
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static uint64_t g_evtRingPhys = 0;
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static uint32_t g_evtRingDequeue = 0;
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static bool g_evtRingCCS = true;
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// Event Ring Segment Table
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static ERSTEntry* g_erst = nullptr;
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static uint64_t g_erstPhys = 0;
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// Command completion tracking
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static volatile bool g_cmdCompleted = false;
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static volatile uint32_t g_cmdCompletionCode = 0;
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volatile uint32_t g_cmdCompletionSlotId = 0; // not static: accessed by UsbDevice.cpp
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// Transfer completion tracking (for EP0 control transfers during init)
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static volatile bool g_xferCompleted = false;
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static volatile uint32_t g_xferCompletionCode = 0;
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// Synchronous bulk transfer tracking. Only one storage-style blocking bulk
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// transfer is active at a time.
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static volatile bool g_syncBulkActive = false;
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static volatile bool g_syncBulkCompleted = false;
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static volatile uint8_t g_syncBulkSlotId = 0;
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static volatile uint8_t g_syncBulkEpDci = 0;
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static volatile uint32_t g_syncBulkLength = 0;
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static volatile uint32_t g_syncBulkResidual = 0;
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static volatile uint32_t g_syncBulkCompletionCode = 0;
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// Per-device info
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static UsbDeviceInfo g_devices[MAX_SLOTS + 1] = {};
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// Interrupt transfer data buffers (per slot)
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static uint8_t* g_interruptDataBuf[MAX_SLOTS + 1] = {};
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static uint64_t g_interruptDataBufPhys[MAX_SLOTS + 1] = {};
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// Bulk IN transfer data buffers (per slot)
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static uint8_t* g_bulkInDataBuf[MAX_SLOTS + 1] = {};
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static uint64_t g_bulkInDataBufPhys[MAX_SLOTS + 1] = {};
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// Transfer callbacks for non-HID class drivers (per slot)
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static TransferCallback g_transferCallbacks[MAX_SLOTS + 1] = {};
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// Scratchpad buffer array
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static uint64_t* g_scratchpadBufs = nullptr;
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// -------------------------------------------------------------------------
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// Register access helpers
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// -------------------------------------------------------------------------
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static void WriteOp(uint32_t reg, uint32_t value) {
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*(volatile uint32_t*)(g_opBase + reg) = value;
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}
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static uint32_t ReadOp(uint32_t reg) {
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return *(volatile uint32_t*)(g_opBase + reg);
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}
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static void WriteRt(uint32_t reg, uint32_t value) {
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*(volatile uint32_t*)(g_rtBase + reg) = value;
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}
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static uint32_t ReadRt(uint32_t reg) {
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return *(volatile uint32_t*)(g_rtBase + reg);
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}
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static uint32_t ReadCap(uint32_t reg) {
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return *(volatile uint32_t*)(g_mmioBase + reg);
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}
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static void WriteDoorbell(uint32_t index, uint32_t value) {
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*(volatile uint32_t*)(g_dbBase + index * 4) = value;
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}
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// -------------------------------------------------------------------------
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// DMA buffer allocation
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// -------------------------------------------------------------------------
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static uint8_t* AllocateDmaBuffer(uint64_t& outPhysAddr) {
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void* virt = Memory::g_pfa->AllocateZeroed();
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outPhysAddr = Memory::SubHHDM(virt);
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return (uint8_t*)virt;
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}
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// -------------------------------------------------------------------------
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// Transfer ring advance helpers (handle Link TRB wrap)
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// -------------------------------------------------------------------------
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// Advance EP0 ring enqueue pointer, activating Link TRB when reached
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static void AdvanceEP0Ring(UsbDeviceInfo& dev) {
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dev.EP0RingEnqueue++;
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if (dev.EP0RingEnqueue >= XFER_RING_SIZE - 1) {
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// Reached Link TRB — set its cycle bit and wrap
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TRB& link = dev.EP0Ring[XFER_RING_SIZE - 1];
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if (dev.EP0RingCCS) {
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link.Control |= TRB_CYCLE_BIT;
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} else {
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link.Control &= ~TRB_CYCLE_BIT;
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}
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dev.EP0RingCCS = !dev.EP0RingCCS;
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dev.EP0RingEnqueue = 0;
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}
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}
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// Advance interrupt ring enqueue pointer, activating Link TRB when reached
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static void AdvanceInterruptRing(UsbDeviceInfo& dev) {
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dev.InterruptRingEnqueue++;
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if (dev.InterruptRingEnqueue >= XFER_RING_SIZE - 1) {
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TRB& link = dev.InterruptRing[XFER_RING_SIZE - 1];
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if (dev.InterruptRingCCS) {
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link.Control |= TRB_CYCLE_BIT;
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} else {
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link.Control &= ~TRB_CYCLE_BIT;
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}
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dev.InterruptRingCCS = !dev.InterruptRingCCS;
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dev.InterruptRingEnqueue = 0;
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}
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}
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// Advance bulk IN ring enqueue pointer, activating Link TRB when reached
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static void AdvanceBulkInRing(UsbDeviceInfo& dev) {
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dev.BulkInRingEnqueue++;
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if (dev.BulkInRingEnqueue >= XFER_RING_SIZE - 1) {
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TRB& link = dev.BulkInRing[XFER_RING_SIZE - 1];
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if (dev.BulkInRingCCS) {
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link.Control |= TRB_CYCLE_BIT;
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} else {
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link.Control &= ~TRB_CYCLE_BIT;
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}
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dev.BulkInRingCCS = !dev.BulkInRingCCS;
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dev.BulkInRingEnqueue = 0;
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}
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}
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// Advance bulk OUT ring enqueue pointer, activating Link TRB when reached
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static void AdvanceBulkOutRing(UsbDeviceInfo& dev) {
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dev.BulkOutRingEnqueue++;
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if (dev.BulkOutRingEnqueue >= XFER_RING_SIZE - 1) {
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TRB& link = dev.BulkOutRing[XFER_RING_SIZE - 1];
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if (dev.BulkOutRingCCS) {
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link.Control |= TRB_CYCLE_BIT;
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} else {
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link.Control &= ~TRB_CYCLE_BIT;
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}
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dev.BulkOutRingCCS = !dev.BulkOutRingCCS;
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dev.BulkOutRingEnqueue = 0;
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}
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}
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// -------------------------------------------------------------------------
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// Forward declarations
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// -------------------------------------------------------------------------
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static void HandleInterrupt(uint8_t irq);
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// -------------------------------------------------------------------------
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// MSI setup (same pattern as E1000E)
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// -------------------------------------------------------------------------
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static bool SetupMsi(uint8_t bus, uint8_t dev, uint8_t func) {
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uint8_t cap = Pci::FindCapability(bus, dev, func, Pci::PCI_CAP_MSI);
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if (cap == 0) {
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KernelLogStream(INFO, "xHCI") << "MSI capability not found";
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return false;
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}
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KernelLogStream(INFO, "xHCI") << "MSI capability at offset " << base::hex << (uint64_t)cap;
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// Read Message Control (cap+2)
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uint16_t msgCtrl = Pci::LegacyRead16(bus, dev, func, cap + 2);
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bool is64bit = (msgCtrl & (1 << 7)) != 0;
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// Write Message Address (cap+4): BSP APIC ID 0, physical destination, fixed delivery
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Pci::LegacyWrite32(bus, dev, func, cap + 4, MSI_ADDR_BASE);
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// Write Message Data (vector number, edge-triggered, fixed delivery)
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if (is64bit) {
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// 64-bit: Upper Address at cap+8, Data at cap+12
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Pci::LegacyWrite32(bus, dev, func, cap + 8, 0);
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Pci::LegacyWrite16(bus, dev, func, cap + 12, MSI_VECTOR);
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} else {
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// 32-bit: Data at cap+8
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Pci::LegacyWrite16(bus, dev, func, cap + 8, MSI_VECTOR);
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}
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// Enable MSI: set bit 0 (MSI Enable), clear bits 6:4 (single message)
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msgCtrl &= ~(0x70); // Clear Multiple Message Enable (bits 6:4)
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msgCtrl |= (1 << 0); // MSI Enable
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Pci::LegacyWrite16(bus, dev, func, cap + 2, msgCtrl);
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// Disable legacy INTx in PCI command register
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uint16_t pciCmd = Pci::LegacyRead16(bus, dev, func, (uint8_t)Pci::PCI_REG_COMMAND);
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pciCmd |= Pci::PCI_CMD_INTX_DISABLE;
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Pci::LegacyWrite16(bus, dev, func, (uint8_t)Pci::PCI_REG_COMMAND, pciCmd);
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// Register the interrupt handler for MSI vector
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Hal::RegisterIrqHandler(MSI_IRQ, HandleInterrupt);
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KernelLogStream(OK, "xHCI") << "MSI enabled: vector " << base::dec << (uint64_t)MSI_VECTOR
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<< " (IRQ slot " << (uint64_t)MSI_IRQ << ")" << (is64bit ? " [64-bit]" : " [32-bit]");
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return true;
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}
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// -------------------------------------------------------------------------
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// PollEvents - process event ring
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// -------------------------------------------------------------------------
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void PollEvents() {
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while (true) {
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TRB& evt = g_evtRing[g_evtRingDequeue];
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// Check if the cycle bit matches our expected cycle state
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bool evtCycle = (evt.Control & TRB_CYCLE_BIT) != 0;
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if (evtCycle != g_evtRingCCS) {
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break; // No more events
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}
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uint32_t trbType = (evt.Control & TRB_TYPE_MASK) >> TRB_TYPE_SHIFT;
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switch (trbType) {
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case TRB_COMMAND_COMPLETION: {
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uint32_t completionCode = (evt.Status >> 24) & 0xFF;
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uint32_t slotId = (evt.Control >> 24) & 0xFF;
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g_cmdCompletionCode = completionCode;
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g_cmdCompletionSlotId = slotId;
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g_cmdCompleted = true;
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break;
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}
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case TRB_PORT_STATUS_CHANGE: {
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uint32_t portId = (evt.Parameter0 >> 24) & 0xFF;
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uint32_t portsc = ReadOp(OP_PORTSC_BASE + (portId - 1) * OP_PORTSC_STRIDE);
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// Clear change bits (write-1-to-clear)
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WriteOp(OP_PORTSC_BASE + (portId - 1) * OP_PORTSC_STRIDE,
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(portsc & PORTSC_PRESERVE) | PORTSC_CHANGE_BITS);
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// Defer enumeration to ProcessDeferredWork outside interrupt context.
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if (g_bootScanComplete && portId >= 1 && portId <= g_maxPorts) {
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g_hotplugPending[portId - 1] = true;
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g_deferredWorkPending = true;
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}
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break;
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}
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case TRB_TRANSFER_EVENT: {
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uint32_t completionCode = (evt.Status >> 24) & 0xFF;
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uint32_t slotId = (evt.Control >> 24) & 0xFF;
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uint32_t epDci = (evt.Control >> 16) & 0x1F;
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uint32_t residual = evt.Status & 0x00FFFFFF;
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if (epDci == 1) {
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// EP0 (DCI 1) - control transfer completion
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g_xferCompletionCode = completionCode;
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g_xferCompleted = true;
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} else if (slotId > 0 && slotId <= MAX_SLOTS && g_devices[slotId].Active) {
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UsbDeviceInfo& dev = g_devices[slotId];
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if (g_syncBulkActive &&
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slotId == g_syncBulkSlotId &&
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epDci == g_syncBulkEpDci) {
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g_syncBulkResidual = residual;
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g_syncBulkCompletionCode = completionCode;
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g_syncBulkCompleted = true;
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break;
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}
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if (completionCode == CC_SUCCESS || completionCode == CC_SHORT_PACKET) {
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// Compute actual transfer length from residual
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// Check if this is a bulk IN endpoint completion
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uint8_t bulkInDci = dev.BulkInEpNum ? (dev.BulkInEpNum * 2 + 1) : 0;
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uint8_t bulkOutDci = dev.BulkOutEpNum ? (dev.BulkOutEpNum * 2) : 0;
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uint8_t intDci = dev.InterruptEpNum ? (dev.InterruptEpNum * 2 + 1) : 0;
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if (epDci == bulkInDci && g_transferCallbacks[slotId]) {
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// Bulk IN — dispatch via registered callback
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uint16_t len = dev.BulkInMaxPacket;
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if (residual < len) len = dev.BulkInMaxPacket - (uint16_t)residual;
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g_transferCallbacks[slotId](slotId, epDci,
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g_bulkInDataBuf[slotId], len, completionCode);
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} else if (epDci == bulkOutDci && g_transferCallbacks[slotId]) {
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// Bulk OUT completion — notify callback
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g_transferCallbacks[slotId](slotId, epDci,
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nullptr, 0, completionCode);
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} else if (epDci == intDci) {
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// Interrupt IN — HID or callback dispatch
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uint16_t len = dev.InterruptMaxPacket;
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if (residual < len) len = dev.InterruptMaxPacket - (uint16_t)residual;
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if (dev.InterfaceClass == UsbDevice::CLASS_HID) {
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if (dev.InterfaceProtocol == UsbDevice::PROTOCOL_KEYBOARD) {
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HidKeyboard::ProcessReport(g_interruptDataBuf[slotId], len);
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} else if (dev.InterfaceProtocol == UsbDevice::PROTOCOL_MOUSE) {
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HidMouse::ProcessReport(g_interruptDataBuf[slotId], len);
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}
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// Re-queue for next HID report
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QueueInterruptTransfer(slotId);
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} else if (g_transferCallbacks[slotId]) {
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// Callback is responsible for re-queuing
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g_transferCallbacks[slotId](slotId, epDci,
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g_interruptDataBuf[slotId], len, completionCode);
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}
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} else if (g_transferCallbacks[slotId]) {
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// Unknown endpoint — try callback
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g_transferCallbacks[slotId](slotId, epDci,
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nullptr, 0, completionCode);
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}
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} else {
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KernelLogStream(WARNING, "xHCI") << "Transfer error on slot "
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<< base::dec << (uint64_t)slotId << " ep " << (uint64_t)epDci
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<< " cc=" << (uint64_t)completionCode;
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// Notify callback of errors too
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if (g_transferCallbacks[slotId]) {
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g_transferCallbacks[slotId](slotId, epDci,
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nullptr, 0, completionCode);
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}
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}
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}
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break;
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}
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default:
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break;
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}
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// Advance dequeue pointer
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g_evtRingDequeue++;
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if (g_evtRingDequeue >= EVT_RING_SIZE) {
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g_evtRingDequeue = 0;
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g_evtRingCCS = !g_evtRingCCS;
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}
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}
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// Update ERDP to tell the controller we have processed events
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// Bit 3 (EHB - Event Handler Busy) must be set to clear it
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uint64_t erdp = g_evtRingPhys + (uint64_t)g_evtRingDequeue * sizeof(TRB);
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erdp |= (1 << 3); // Set EHB to clear it
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WriteRt(IR0_ERDP, (uint32_t)(erdp & 0xFFFFFFFF));
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WriteRt(IR0_ERDP + 4, (uint32_t)(erdp >> 32));
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}
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// -------------------------------------------------------------------------
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// HandleInterrupt
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// -------------------------------------------------------------------------
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static void HandleInterrupt(uint8_t irq) {
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(void)irq;
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// Clear USBSTS.EINT only (don't accidentally clear other W1C bits)
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WriteOp(OP_USBSTS, USBSTS_EINT);
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// Clear IMAN.IP and ensure IE stays enabled
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WriteRt(IR0_IMAN, IMAN_IP | IMAN_IE);
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PollEvents();
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}
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// -------------------------------------------------------------------------
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// SendCommand - send a command TRB on the command ring
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// -------------------------------------------------------------------------
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uint32_t SendCommand(const TRB& trb) {
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// Place TRB at current enqueue position
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TRB& slot = g_cmdRing[g_cmdRingEnqueue];
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slot.Parameter0 = trb.Parameter0;
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slot.Parameter1 = trb.Parameter1;
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slot.Status = trb.Status;
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// Set the type and cycle bit in control
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uint32_t control = trb.Control & ~TRB_CYCLE_BIT;
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if (g_cmdRingCCS) {
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control |= TRB_CYCLE_BIT;
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}
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slot.Control = control;
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// Advance enqueue pointer
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g_cmdRingEnqueue++;
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if (g_cmdRingEnqueue >= CMD_RING_SIZE - 1) {
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// We've reached the Link TRB - toggle its cycle bit and wrap
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TRB& link = g_cmdRing[CMD_RING_SIZE - 1];
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// Update the link TRB cycle bit to match current CCS
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if (g_cmdRingCCS) {
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link.Control |= TRB_CYCLE_BIT;
|
|
} else {
|
|
link.Control &= ~TRB_CYCLE_BIT;
|
|
}
|
|
g_cmdRingCCS = !g_cmdRingCCS;
|
|
g_cmdRingEnqueue = 0;
|
|
}
|
|
|
|
// Clear completion flag and ring the host controller doorbell
|
|
g_cmdCompleted = false;
|
|
WriteDoorbell(0, 0);
|
|
|
|
// Poll until command completes (with timeout)
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
PollEvents();
|
|
if (g_cmdCompleted) {
|
|
return g_cmdCompletionCode;
|
|
}
|
|
// Small delay
|
|
for (int j = 0; j < 100; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
KernelLogStream(WARNING, "xHCI") << "Command timeout";
|
|
return 0xFF;
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// ControlTransfer - perform a control transfer on EP0
|
|
// -------------------------------------------------------------------------
|
|
|
|
uint32_t ControlTransfer(uint8_t slotId, uint8_t bmRequestType, uint8_t bRequest,
|
|
uint16_t wValue, uint16_t wIndex, uint16_t wLength,
|
|
void* data, bool dirIn) {
|
|
|
|
if (slotId == 0 || slotId > MAX_SLOTS || !g_devices[slotId].Active) {
|
|
return 0xFF;
|
|
}
|
|
|
|
UsbDeviceInfo& dev = g_devices[slotId];
|
|
|
|
// --- Setup Stage TRB ---
|
|
TRB& setup = dev.EP0Ring[dev.EP0RingEnqueue];
|
|
setup.Parameter0 = (uint32_t)bmRequestType | ((uint32_t)bRequest << 8) | ((uint32_t)wValue << 16);
|
|
setup.Parameter1 = (uint32_t)wIndex | ((uint32_t)wLength << 16);
|
|
setup.Status = 8; // Setup packet is always 8 bytes
|
|
|
|
uint32_t setupControl = (TRB_SETUP_STAGE << TRB_TYPE_SHIFT) | TRB_IDT;
|
|
if (wLength > 0) {
|
|
setupControl |= dirIn ? TRB_TRT_IN : TRB_TRT_OUT;
|
|
} else {
|
|
setupControl |= TRB_TRT_NODATA;
|
|
}
|
|
if (dev.EP0RingCCS) {
|
|
setupControl |= TRB_CYCLE_BIT;
|
|
}
|
|
setup.Control = setupControl;
|
|
|
|
// Advance EP0 enqueue (handles Link TRB wrap)
|
|
AdvanceEP0Ring(dev);
|
|
|
|
// --- Data Stage TRB (if wLength > 0) ---
|
|
if (wLength > 0 && data != nullptr) {
|
|
uint64_t dataPhys = Memory::SubHHDM(data);
|
|
|
|
TRB& dataTrb = dev.EP0Ring[dev.EP0RingEnqueue];
|
|
dataTrb.Parameter0 = (uint32_t)(dataPhys & 0xFFFFFFFF);
|
|
dataTrb.Parameter1 = (uint32_t)(dataPhys >> 32);
|
|
dataTrb.Status = wLength;
|
|
|
|
uint32_t dataControl = (TRB_DATA_STAGE << TRB_TYPE_SHIFT);
|
|
if (dirIn) {
|
|
dataControl |= TRB_DIR_IN;
|
|
}
|
|
if (dev.EP0RingCCS) {
|
|
dataControl |= TRB_CYCLE_BIT;
|
|
}
|
|
dataTrb.Control = dataControl;
|
|
|
|
AdvanceEP0Ring(dev);
|
|
}
|
|
|
|
// --- Status Stage TRB ---
|
|
TRB& status = dev.EP0Ring[dev.EP0RingEnqueue];
|
|
status.Parameter0 = 0;
|
|
status.Parameter1 = 0;
|
|
status.Status = 0;
|
|
|
|
// Status stage direction is opposite of data stage
|
|
uint32_t statusControl = (TRB_STATUS_STAGE << TRB_TYPE_SHIFT) | TRB_IOC;
|
|
if (wLength > 0 && !dirIn) {
|
|
statusControl |= TRB_DIR_IN;
|
|
} else if (wLength == 0) {
|
|
statusControl |= TRB_DIR_IN;
|
|
}
|
|
if (dev.EP0RingCCS) {
|
|
statusControl |= TRB_CYCLE_BIT;
|
|
}
|
|
status.Control = statusControl;
|
|
|
|
AdvanceEP0Ring(dev);
|
|
|
|
// Ring doorbell for this slot, target EP0 (DCI 1)
|
|
g_xferCompleted = false;
|
|
WriteDoorbell(slotId, 1);
|
|
|
|
// Poll until transfer completes
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
PollEvents();
|
|
if (g_xferCompleted) {
|
|
return g_xferCompletionCode;
|
|
}
|
|
for (int j = 0; j < 100; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
KernelLogStream(WARNING, "xHCI") << "Control transfer timeout on slot " << base::dec << (uint64_t)slotId;
|
|
|
|
// Recover EP0 ring: Stop Endpoint, then Set TR Dequeue Pointer
|
|
// so that subsequent control transfers on this slot still work.
|
|
TRB stopTrb = {};
|
|
stopTrb.Control = (TRB_STOP_ENDPOINT << TRB_TYPE_SHIFT)
|
|
| ((uint32_t)slotId << 24)
|
|
| (1 << 16); // DCI=1 (EP0) in bits 20:16
|
|
SendCommand(stopTrb);
|
|
|
|
// Reset the enqueue pointer to the start and set the dequeue pointer
|
|
// to match so the ring is back in sync.
|
|
uint64_t newDeq = dev.EP0RingPhys
|
|
+ (uint64_t)dev.EP0RingEnqueue * sizeof(TRB);
|
|
if (dev.EP0RingCCS) {
|
|
newDeq |= 1; // DCS bit
|
|
}
|
|
|
|
TRB deqTrb = {};
|
|
deqTrb.Parameter0 = (uint32_t)(newDeq & 0xFFFFFFFF);
|
|
deqTrb.Parameter1 = (uint32_t)(newDeq >> 32);
|
|
deqTrb.Control = (TRB_SET_TR_DEQUEUE << TRB_TYPE_SHIFT)
|
|
| ((uint32_t)slotId << 24)
|
|
| (1 << 16); // DCI=1 (EP0)
|
|
SendCommand(deqTrb);
|
|
|
|
return 0xFF;
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// QueueInterruptTransfer
|
|
// -------------------------------------------------------------------------
|
|
|
|
void QueueInterruptTransfer(uint8_t slotId) {
|
|
if (slotId == 0 || slotId > MAX_SLOTS || !g_devices[slotId].Active) {
|
|
return;
|
|
}
|
|
|
|
UsbDeviceInfo& dev = g_devices[slotId];
|
|
|
|
// Allocate interrupt data buffer if not yet allocated
|
|
if (g_interruptDataBuf[slotId] == nullptr) {
|
|
g_interruptDataBuf[slotId] = AllocateDmaBuffer(g_interruptDataBufPhys[slotId]);
|
|
}
|
|
|
|
// Build a Normal TRB on the interrupt ring
|
|
TRB& trb = dev.InterruptRing[dev.InterruptRingEnqueue];
|
|
trb.Parameter0 = (uint32_t)(g_interruptDataBufPhys[slotId] & 0xFFFFFFFF);
|
|
trb.Parameter1 = (uint32_t)(g_interruptDataBufPhys[slotId] >> 32);
|
|
trb.Status = dev.InterruptMaxPacket;
|
|
|
|
uint32_t control = (TRB_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC | TRB_ISP;
|
|
if (dev.InterruptRingCCS) {
|
|
control |= TRB_CYCLE_BIT;
|
|
}
|
|
trb.Control = control;
|
|
|
|
// Advance enqueue (handles Link TRB wrap)
|
|
AdvanceInterruptRing(dev);
|
|
|
|
// Ring doorbell: target = (InterruptEpNum * 2 + 1) for IN endpoint DCI
|
|
uint8_t target = dev.InterruptEpNum * 2 + 1;
|
|
WriteDoorbell(slotId, target);
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// QueueBulkInTransfer
|
|
// -------------------------------------------------------------------------
|
|
|
|
void QueueBulkInTransfer(uint8_t slotId, uint8_t* data, uint64_t dataPhys, uint32_t length) {
|
|
if (slotId == 0 || slotId > MAX_SLOTS || !g_devices[slotId].Active) return;
|
|
|
|
UsbDeviceInfo& dev = g_devices[slotId];
|
|
if (!dev.BulkInRing || dev.BulkInEpNum == 0) return;
|
|
|
|
// If caller provides nullptr, use the per-slot bulk IN DMA buffer
|
|
if (data == nullptr) {
|
|
if (g_bulkInDataBuf[slotId] == nullptr) {
|
|
g_bulkInDataBuf[slotId] = AllocateDmaBuffer(g_bulkInDataBufPhys[slotId]);
|
|
}
|
|
data = g_bulkInDataBuf[slotId];
|
|
dataPhys = g_bulkInDataBufPhys[slotId];
|
|
}
|
|
|
|
TRB& trb = dev.BulkInRing[dev.BulkInRingEnqueue];
|
|
trb.Parameter0 = (uint32_t)(dataPhys & 0xFFFFFFFF);
|
|
trb.Parameter1 = (uint32_t)(dataPhys >> 32);
|
|
trb.Status = length;
|
|
|
|
uint32_t control = (TRB_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC | TRB_ISP;
|
|
if (dev.BulkInRingCCS) {
|
|
control |= TRB_CYCLE_BIT;
|
|
}
|
|
trb.Control = control;
|
|
|
|
AdvanceBulkInRing(dev);
|
|
|
|
// Ring doorbell: DCI for bulk IN = EpNum * 2 + 1
|
|
uint8_t target = dev.BulkInEpNum * 2 + 1;
|
|
WriteDoorbell(slotId, target);
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// QueueBulkOutTransfer
|
|
// -------------------------------------------------------------------------
|
|
|
|
void QueueBulkOutTransfer(uint8_t slotId, uint8_t* data, uint64_t dataPhys, uint32_t length) {
|
|
if (slotId == 0 || slotId > MAX_SLOTS || !g_devices[slotId].Active) return;
|
|
|
|
UsbDeviceInfo& dev = g_devices[slotId];
|
|
if (!dev.BulkOutRing || dev.BulkOutEpNum == 0) return;
|
|
|
|
TRB& trb = dev.BulkOutRing[dev.BulkOutRingEnqueue];
|
|
trb.Parameter0 = (uint32_t)(dataPhys & 0xFFFFFFFF);
|
|
trb.Parameter1 = (uint32_t)(dataPhys >> 32);
|
|
trb.Status = length;
|
|
|
|
uint32_t control = (TRB_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC;
|
|
if (dev.BulkOutRingCCS) {
|
|
control |= TRB_CYCLE_BIT;
|
|
}
|
|
trb.Control = control;
|
|
|
|
AdvanceBulkOutRing(dev);
|
|
|
|
// Ring doorbell: DCI for bulk OUT = EpNum * 2
|
|
uint8_t target = dev.BulkOutEpNum * 2;
|
|
WriteDoorbell(slotId, target);
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// BulkTransfer - blocking bulk IN/OUT transfer
|
|
// -------------------------------------------------------------------------
|
|
|
|
uint32_t BulkTransfer(uint8_t slotId, bool dirIn, void* data, uint64_t dataPhys,
|
|
uint32_t length, uint32_t* actualLength) {
|
|
if (actualLength) *actualLength = 0;
|
|
if (length == 0) return CC_SUCCESS;
|
|
if (length > 0x10000) return 0xFF;
|
|
if (slotId == 0 || slotId > MAX_SLOTS || !g_devices[slotId].Active) return 0xFF;
|
|
if (data == nullptr) return 0xFF;
|
|
if (g_syncBulkActive) return 0xFF;
|
|
|
|
UsbDeviceInfo& dev = g_devices[slotId];
|
|
if (dataPhys == 0) dataPhys = Memory::SubHHDM(data);
|
|
|
|
uint8_t target = 0;
|
|
|
|
if (dirIn) {
|
|
if (!dev.BulkInRing || dev.BulkInEpNum == 0) return 0xFF;
|
|
|
|
TRB& trb = dev.BulkInRing[dev.BulkInRingEnqueue];
|
|
trb.Parameter0 = (uint32_t)(dataPhys & 0xFFFFFFFF);
|
|
trb.Parameter1 = (uint32_t)(dataPhys >> 32);
|
|
trb.Status = length;
|
|
|
|
uint32_t control = (TRB_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC | TRB_ISP;
|
|
if (dev.BulkInRingCCS) control |= TRB_CYCLE_BIT;
|
|
trb.Control = control;
|
|
|
|
AdvanceBulkInRing(dev);
|
|
target = dev.BulkInEpNum * 2 + 1;
|
|
} else {
|
|
if (!dev.BulkOutRing || dev.BulkOutEpNum == 0) return 0xFF;
|
|
|
|
TRB& trb = dev.BulkOutRing[dev.BulkOutRingEnqueue];
|
|
trb.Parameter0 = (uint32_t)(dataPhys & 0xFFFFFFFF);
|
|
trb.Parameter1 = (uint32_t)(dataPhys >> 32);
|
|
trb.Status = length;
|
|
|
|
uint32_t control = (TRB_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC;
|
|
if (dev.BulkOutRingCCS) control |= TRB_CYCLE_BIT;
|
|
trb.Control = control;
|
|
|
|
AdvanceBulkOutRing(dev);
|
|
target = dev.BulkOutEpNum * 2;
|
|
}
|
|
|
|
g_syncBulkSlotId = slotId;
|
|
g_syncBulkEpDci = target;
|
|
g_syncBulkLength = length;
|
|
g_syncBulkResidual = length;
|
|
g_syncBulkCompletionCode = 0;
|
|
g_syncBulkCompleted = false;
|
|
g_syncBulkActive = true;
|
|
|
|
WriteDoorbell(slotId, target);
|
|
|
|
uint64_t start = Timekeeping::GetMilliseconds();
|
|
while (Timekeeping::GetMilliseconds() - start < 5000) {
|
|
PollEvents();
|
|
if (g_syncBulkCompleted) {
|
|
uint32_t cc = g_syncBulkCompletionCode;
|
|
uint32_t residual = g_syncBulkResidual;
|
|
g_syncBulkActive = false;
|
|
|
|
if (actualLength) {
|
|
*actualLength = (residual < g_syncBulkLength)
|
|
? (g_syncBulkLength - residual)
|
|
: 0;
|
|
}
|
|
return cc;
|
|
}
|
|
|
|
for (int j = 0; j < 100; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
g_syncBulkActive = false;
|
|
KernelLogStream(WARNING, "xHCI") << "Bulk transfer timeout on slot "
|
|
<< base::dec << (uint64_t)slotId << " ep " << (uint64_t)target;
|
|
return 0xFF;
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// RegisterTransferCallback
|
|
// -------------------------------------------------------------------------
|
|
|
|
void RegisterTransferCallback(uint8_t slotId, TransferCallback cb) {
|
|
if (slotId > 0 && slotId <= MAX_SLOTS) {
|
|
g_transferCallbacks[slotId] = cb;
|
|
}
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// RingDoorbell
|
|
// -------------------------------------------------------------------------
|
|
|
|
void RingDoorbell(uint8_t slotId, uint8_t target) {
|
|
WriteDoorbell(slotId, target);
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// GetDevice
|
|
// -------------------------------------------------------------------------
|
|
|
|
UsbDeviceInfo* GetDevice(uint8_t slotId) {
|
|
if (slotId == 0 || slotId > MAX_SLOTS) {
|
|
return nullptr;
|
|
}
|
|
return &g_devices[slotId];
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// IsInitialized
|
|
// -------------------------------------------------------------------------
|
|
|
|
bool IsInitialized() {
|
|
return g_initialized;
|
|
}
|
|
|
|
bool HasDeferredWork() {
|
|
return g_initialized && g_deferredWorkPending;
|
|
}
|
|
|
|
static void UnregisterClassDriver(uint8_t slotId, const UsbDeviceInfo& dev) {
|
|
if (dev.InterfaceClass == UsbDevice::CLASS_MASS_STORAGE) {
|
|
MassStorage::UnregisterDevice(slotId);
|
|
} else if (dev.InterfaceClass == UsbDevice::CLASS_HID &&
|
|
dev.InterfaceProtocol == UsbDevice::PROTOCOL_KEYBOARD) {
|
|
HidKeyboard::UnregisterDevice(slotId);
|
|
} else if (dev.InterfaceClass == UsbDevice::CLASS_HID &&
|
|
dev.InterfaceProtocol == UsbDevice::PROTOCOL_MOUSE) {
|
|
HidMouse::UnregisterDevice(slotId);
|
|
}
|
|
}
|
|
|
|
static void DisableSlot(uint8_t slotId) {
|
|
TRB trb = {};
|
|
trb.Control = (TRB_DISABLE_SLOT << TRB_TYPE_SHIFT)
|
|
| ((uint32_t)slotId << 24);
|
|
|
|
uint32_t cc = SendCommand(trb);
|
|
if (cc != CC_SUCCESS) {
|
|
KernelLogStream(WARNING, "xHCI") << "Disable Slot failed for slot "
|
|
<< base::dec << (uint64_t)slotId << " cc=" << (uint64_t)cc;
|
|
}
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// ProcessDeferredWork - handle hot-plug outside interrupt context.
|
|
// Called from the BSP idle path so class-driver probing can wait on timers.
|
|
// -------------------------------------------------------------------------
|
|
|
|
void ProcessDeferredWork() {
|
|
if (!g_initialized || !g_bootScanComplete || !g_deferredWorkPending) return;
|
|
|
|
// CAS claim: any idle core may call this, but only one runs at a time.
|
|
// AcquireTransport in MassStorage handles the SCSI-in-flight case itself.
|
|
bool expected = false;
|
|
if (!g_hotplugProcessing.compare_exchange_strong(expected, true,
|
|
std::memory_order_acquire, std::memory_order_relaxed)) {
|
|
return;
|
|
}
|
|
g_deferredWorkPending = false;
|
|
|
|
for (uint32_t port = 0; port < g_maxPorts; port++) {
|
|
if (!g_hotplugPending[port]) continue;
|
|
g_hotplugPending[port] = false;
|
|
|
|
uint32_t portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
|
|
if (portsc & PORTSC_CCS) {
|
|
// Device connected — check if already assigned to a slot
|
|
bool alreadyActive = false;
|
|
for (uint8_t s = 1; s <= MAX_SLOTS; s++) {
|
|
if (g_devices[s].Active && g_devices[s].PortId == port + 1) {
|
|
alreadyActive = true;
|
|
break;
|
|
}
|
|
}
|
|
if (alreadyActive) continue;
|
|
|
|
if (portsc & PORTSC_PED) {
|
|
// Already enabled — enumerate after recovery delay
|
|
uint32_t speed = (portsc >> 10) & 0xF;
|
|
BusyWaitMs(10);
|
|
UsbDevice::EnumerateDevice(port + 1, speed);
|
|
} else {
|
|
// Need port reset first
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_PR | PORTSC_CHANGE_BITS);
|
|
|
|
bool resetDone = false;
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
PollEvents();
|
|
uint32_t ps = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (ps & PORTSC_PRC) {
|
|
resetDone = true;
|
|
break;
|
|
}
|
|
for (int j = 0; j < 100; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
if (!resetDone) {
|
|
KernelLogStream(WARNING, "xHCI") << "Hot-plug: port "
|
|
<< base::dec << (uint64_t)(port + 1) << " reset timeout";
|
|
continue;
|
|
}
|
|
|
|
portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
uint32_t speed = (portsc >> 10) & 0xF;
|
|
|
|
// Clear change bits
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_CHANGE_BITS);
|
|
|
|
// Post-reset recovery delay (USB spec requires >= 10ms)
|
|
BusyWaitMs(10);
|
|
|
|
UsbDevice::EnumerateDevice(port + 1, speed);
|
|
}
|
|
} else {
|
|
// Device disconnected — deactivate its slot
|
|
for (uint8_t s = 1; s <= MAX_SLOTS; s++) {
|
|
if (g_devices[s].Active && g_devices[s].PortId == port + 1) {
|
|
UnregisterClassDriver(s, g_devices[s]);
|
|
g_devices[s].Active = false;
|
|
g_transferCallbacks[s] = nullptr;
|
|
DisableSlot(s);
|
|
g_dcbaa[s] = 0;
|
|
g_devices[s] = {};
|
|
KernelLogStream(INFO, "xHCI") << "Hot-unplug: slot "
|
|
<< base::dec << (uint64_t)s << " (port "
|
|
<< (uint64_t)(port + 1) << ") deactivated";
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
g_hotplugProcessing.store(false, std::memory_order_release);
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Probe (called by PCI driver matching framework)
|
|
// -------------------------------------------------------------------------
|
|
|
|
bool Probe(const Pci::PciDevice& dev) {
|
|
if (g_initialized) return false;
|
|
|
|
KernelLogStream(OK, "xHCI") << "Found controller at PCI "
|
|
<< base::hex << (uint64_t)dev.Bus << ":"
|
|
<< (uint64_t)dev.Device << "." << (uint64_t)dev.Function;
|
|
|
|
// Read BAR0 and map MMIO region
|
|
uint64_t mmioPhys = Pci::ReadBar0(dev.Bus, dev.Device, dev.Function);
|
|
|
|
KernelLogStream(INFO, "xHCI") << "BAR0 physical: " << base::hex << mmioPhys;
|
|
|
|
constexpr uint64_t MmioSize = 0x10000;
|
|
for (uint64_t offset = 0; offset < MmioSize; offset += 0x1000) {
|
|
Memory::VMM::g_paging->MapMMIO(mmioPhys + offset, Memory::HHDM(mmioPhys + offset));
|
|
}
|
|
|
|
g_mmioBase = (volatile uint8_t*)Memory::HHDM(mmioPhys);
|
|
|
|
Pci::EnableBusMaster(dev.Bus, dev.Device, dev.Function);
|
|
KernelLogStream(OK, "xHCI") << "Bus mastering enabled";
|
|
|
|
// Parse capability registers
|
|
g_capLength = *(volatile uint8_t*)(g_mmioBase + CAP_CAPLENGTH);
|
|
|
|
uint32_t hciVersion = *(volatile uint16_t*)(g_mmioBase + CAP_HCIVERSION);
|
|
KernelLogStream(INFO, "xHCI") << "Version: " << base::hex << (uint64_t)hciVersion
|
|
<< ", CapLength: " << (uint64_t)g_capLength;
|
|
|
|
uint32_t hcsParams1 = ReadCap(CAP_HCSPARAMS1);
|
|
g_maxSlots = hcsParams1 & 0xFF;
|
|
g_maxPorts = (hcsParams1 >> 24) & 0xFF;
|
|
|
|
uint32_t hcsParams2 = ReadCap(CAP_HCSPARAMS2);
|
|
uint32_t scratchpadBufsHi = (hcsParams2 >> 21) & 0x1F;
|
|
uint32_t scratchpadBufsLo = (hcsParams2 >> 27) & 0x1F;
|
|
uint32_t maxScratchpadBufs = (scratchpadBufsHi << 5) | scratchpadBufsLo;
|
|
|
|
uint32_t dbOff = ReadCap(CAP_DBOFF) & ~0x3u;
|
|
uint32_t rtsOff = ReadCap(CAP_RTSOFF) & ~0x1Fu;
|
|
|
|
g_opBase = g_mmioBase + g_capLength;
|
|
g_rtBase = g_mmioBase + rtsOff;
|
|
g_dbBase = g_mmioBase + dbOff;
|
|
|
|
KernelLogStream(INFO, "xHCI") << "MaxSlots: " << base::dec << (uint64_t)g_maxSlots
|
|
<< ", MaxPorts: " << (uint64_t)g_maxPorts
|
|
<< ", ScratchpadBufs: " << (uint64_t)maxScratchpadBufs;
|
|
|
|
if (g_maxSlots > MAX_SLOTS) g_maxSlots = MAX_SLOTS;
|
|
if (g_maxPorts > MAX_PORTS) g_maxPorts = MAX_PORTS;
|
|
|
|
// Halt controller
|
|
uint32_t usbcmd = ReadOp(OP_USBCMD);
|
|
usbcmd &= ~USBCMD_RS;
|
|
WriteOp(OP_USBCMD, usbcmd);
|
|
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (ReadOp(OP_USBSTS) & USBSTS_HCH) break;
|
|
for (int j = 0; j < 10; j++) asm volatile("" ::: "memory");
|
|
}
|
|
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_HCH)) {
|
|
KernelLogStream(WARNING, "xHCI") << "Controller failed to halt";
|
|
}
|
|
KernelLogStream(OK, "xHCI") << "Controller halted";
|
|
|
|
// Reset controller
|
|
WriteOp(OP_USBCMD, USBCMD_HCRST);
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBCMD) & USBCMD_HCRST)) break;
|
|
for (int j = 0; j < 10; j++) asm volatile("" ::: "memory");
|
|
}
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_CNR)) break;
|
|
for (int j = 0; j < 10; j++) asm volatile("" ::: "memory");
|
|
}
|
|
if (ReadOp(OP_USBSTS) & USBSTS_CNR) {
|
|
KernelLogStream(WARNING, "xHCI") << "Controller not ready after reset";
|
|
}
|
|
KernelLogStream(OK, "xHCI") << "Controller reset complete";
|
|
|
|
// Program CONFIG
|
|
WriteOp(OP_CONFIG, g_maxSlots);
|
|
|
|
// Allocate DCBAA
|
|
g_dcbaa = (uint64_t*)AllocateDmaBuffer(g_dcbaaPhys);
|
|
WriteOp(OP_DCBAAP, (uint32_t)(g_dcbaaPhys & 0xFFFFFFFF));
|
|
WriteOp(OP_DCBAAP + 4, (uint32_t)(g_dcbaaPhys >> 32));
|
|
KernelLogStream(OK, "xHCI") << "DCBAA at phys " << base::hex << g_dcbaaPhys;
|
|
|
|
// Scratchpad buffers
|
|
if (maxScratchpadBufs > 0) {
|
|
uint64_t spArrayPhys;
|
|
g_scratchpadBufs = (uint64_t*)AllocateDmaBuffer(spArrayPhys);
|
|
for (uint32_t i = 0; i < maxScratchpadBufs; i++) {
|
|
uint64_t bufPhys;
|
|
AllocateDmaBuffer(bufPhys);
|
|
g_scratchpadBufs[i] = bufPhys;
|
|
}
|
|
g_dcbaa[0] = spArrayPhys;
|
|
KernelLogStream(OK, "xHCI") << "Allocated " << base::dec << (uint64_t)maxScratchpadBufs << " scratchpad buffers";
|
|
}
|
|
|
|
// Command ring
|
|
g_cmdRing = (TRB*)AllocateDmaBuffer(g_cmdRingPhys);
|
|
TRB& linkTrb = g_cmdRing[CMD_RING_SIZE - 1];
|
|
linkTrb.Parameter0 = (uint32_t)(g_cmdRingPhys & 0xFFFFFFFF);
|
|
linkTrb.Parameter1 = (uint32_t)(g_cmdRingPhys >> 32);
|
|
linkTrb.Status = 0;
|
|
linkTrb.Control = (TRB_LINK << TRB_TYPE_SHIFT) | TRB_ENT;
|
|
uint64_t crcr = g_cmdRingPhys | TRB_CYCLE_BIT;
|
|
WriteOp(OP_CRCR, (uint32_t)(crcr & 0xFFFFFFFF));
|
|
WriteOp(OP_CRCR + 4, (uint32_t)(crcr >> 32));
|
|
g_cmdRingCCS = true;
|
|
g_cmdRingEnqueue = 0;
|
|
KernelLogStream(OK, "xHCI") << "Command ring at phys " << base::hex << g_cmdRingPhys;
|
|
|
|
// Event ring + ERST
|
|
g_evtRing = (TRB*)AllocateDmaBuffer(g_evtRingPhys);
|
|
g_erst = (ERSTEntry*)AllocateDmaBuffer(g_erstPhys);
|
|
g_erst[0].RingSegmentBase = g_evtRingPhys;
|
|
g_erst[0].RingSegmentSize = EVT_RING_SIZE;
|
|
g_erst[0].Reserved = 0;
|
|
WriteRt(IR0_ERSTSZ, 1);
|
|
WriteRt(IR0_ERDP, (uint32_t)(g_evtRingPhys & 0xFFFFFFFF));
|
|
WriteRt(IR0_ERDP + 4, (uint32_t)(g_evtRingPhys >> 32));
|
|
WriteRt(IR0_ERSTBA, (uint32_t)(g_erstPhys & 0xFFFFFFFF));
|
|
WriteRt(IR0_ERSTBA + 4, (uint32_t)(g_erstPhys >> 32));
|
|
g_evtRingCCS = true;
|
|
g_evtRingDequeue = 0;
|
|
KernelLogStream(OK, "xHCI") << "Event ring at phys " << base::hex << g_evtRingPhys;
|
|
|
|
// MSI setup
|
|
if (!SetupMsi(dev.Bus, dev.Device, dev.Function)) {
|
|
KernelLogStream(WARNING, "xHCI") << "MSI not available, using poll mode";
|
|
}
|
|
|
|
// Enable interrupter 0
|
|
WriteRt(IR0_IMAN, IMAN_IE);
|
|
WriteRt(IR0_IMOD, IMOD_INTERVAL_100US);
|
|
|
|
// Start controller
|
|
WriteOp(OP_USBCMD, USBCMD_RS | USBCMD_INTE | USBCMD_HSEE);
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_HCH)) break;
|
|
for (int j = 0; j < 10; j++) asm volatile("" ::: "memory");
|
|
}
|
|
KernelLogStream(OK, "xHCI") << "Controller started";
|
|
g_initialized = true;
|
|
|
|
// Power on all ports
|
|
for (uint32_t port = 0; port < g_maxPorts; port++) {
|
|
uint32_t portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (!(portsc & PORTSC_PP)) {
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE, PORTSC_PP);
|
|
}
|
|
}
|
|
BusyWaitMs(20);
|
|
KernelLogStream(OK, "xHCI") << "All ports powered";
|
|
|
|
// Port scanning
|
|
for (uint32_t port = 0; port < g_maxPorts; port++) {
|
|
uint32_t portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (!(portsc & PORTSC_CCS)) continue;
|
|
|
|
KernelLogStream(INFO, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1)
|
|
<< ": device connected, PORTSC=" << base::hex << (uint64_t)portsc;
|
|
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_PR | PORTSC_CHANGE_BITS);
|
|
|
|
bool resetDone = false;
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
PollEvents();
|
|
uint32_t ps = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (ps & PORTSC_PRC) { resetDone = true; break; }
|
|
for (int j = 0; j < 100; j++) asm volatile("" ::: "memory");
|
|
}
|
|
|
|
if (!resetDone) {
|
|
KernelLogStream(WARNING, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1) << " reset timeout";
|
|
continue;
|
|
}
|
|
|
|
portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
uint32_t speed = (portsc >> 10) & 0xF;
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_CHANGE_BITS);
|
|
|
|
const char* speedStr = "Unknown";
|
|
switch (speed) {
|
|
case SPEED_FULL: speedStr = "Full (12 Mbps)"; break;
|
|
case SPEED_LOW: speedStr = "Low (1.5 Mbps)"; break;
|
|
case SPEED_HIGH: speedStr = "High (480 Mbps)"; break;
|
|
case SPEED_SUPER: speedStr = "Super (5 Gbps)"; break;
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1)
|
|
<< ": reset complete, speed=" << speedStr;
|
|
|
|
BusyWaitMs(10);
|
|
UsbDevice::EnumerateDevice(port + 1, speed);
|
|
}
|
|
|
|
g_bootScanComplete = true;
|
|
KernelLogStream(OK, "xHCI") << "Initialization complete";
|
|
return true;
|
|
}
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Initialize (standalone fallback path)
|
|
// -------------------------------------------------------------------------
|
|
|
|
void Initialize() {
|
|
KernelLogStream(INFO, "xHCI") << "Scanning for xHCI controller...";
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 1: Find xHCI controller on PCI bus
|
|
// -----------------------------------------------------------------
|
|
auto& devices = Pci::GetDevices();
|
|
const Pci::PciDevice* foundDev = nullptr;
|
|
|
|
for (uint64_t i = 0; i < devices.size(); i++) {
|
|
if (devices[i].ClassCode == PCI_CLASS_SERIAL &&
|
|
devices[i].SubClass == PCI_SUBCLASS_USB &&
|
|
devices[i].ProgIf == PCI_PROGIF_XHCI) {
|
|
foundDev = &devices[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (foundDev == nullptr) {
|
|
KernelLogStream(WARNING, "xHCI") << "No xHCI controller found";
|
|
return;
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Found controller at PCI "
|
|
<< base::hex << (uint64_t)foundDev->Bus << ":"
|
|
<< (uint64_t)foundDev->Device << "." << (uint64_t)foundDev->Function;
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 2: Read BAR0 and map MMIO region
|
|
// -----------------------------------------------------------------
|
|
uint64_t mmioPhys = Pci::ReadBar0(foundDev->Bus, foundDev->Device, foundDev->Function);
|
|
|
|
KernelLogStream(INFO, "xHCI") << "BAR0 physical: " << base::hex << mmioPhys;
|
|
|
|
// Map 64KB (16 pages) of MMIO space
|
|
constexpr uint64_t MmioSize = 0x10000;
|
|
for (uint64_t offset = 0; offset < MmioSize; offset += 0x1000) {
|
|
Memory::VMM::g_paging->MapMMIO(mmioPhys + offset, Memory::HHDM(mmioPhys + offset));
|
|
}
|
|
|
|
g_mmioBase = (volatile uint8_t*)Memory::HHDM(mmioPhys);
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 3: Enable PCI bus master and memory space
|
|
// -----------------------------------------------------------------
|
|
Pci::EnableBusMaster(foundDev->Bus, foundDev->Device, foundDev->Function);
|
|
|
|
KernelLogStream(OK, "xHCI") << "Bus mastering enabled";
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 4: Parse capability registers
|
|
// -----------------------------------------------------------------
|
|
g_capLength = *(volatile uint8_t*)(g_mmioBase + CAP_CAPLENGTH);
|
|
|
|
uint32_t hciVersion = *(volatile uint16_t*)(g_mmioBase + CAP_HCIVERSION);
|
|
KernelLogStream(INFO, "xHCI") << "Version: " << base::hex << (uint64_t)hciVersion
|
|
<< ", CapLength: " << (uint64_t)g_capLength;
|
|
|
|
uint32_t hcsParams1 = ReadCap(CAP_HCSPARAMS1);
|
|
g_maxSlots = hcsParams1 & 0xFF;
|
|
g_maxPorts = (hcsParams1 >> 24) & 0xFF;
|
|
|
|
uint32_t hcsParams2 = ReadCap(CAP_HCSPARAMS2);
|
|
uint32_t scratchpadBufsHi = (hcsParams2 >> 21) & 0x1F;
|
|
uint32_t scratchpadBufsLo = (hcsParams2 >> 27) & 0x1F;
|
|
uint32_t maxScratchpadBufs = (scratchpadBufsHi << 5) | scratchpadBufsLo;
|
|
|
|
uint32_t dbOff = ReadCap(CAP_DBOFF) & ~0x3u;
|
|
uint32_t rtsOff = ReadCap(CAP_RTSOFF) & ~0x1Fu;
|
|
|
|
g_opBase = g_mmioBase + g_capLength;
|
|
g_rtBase = g_mmioBase + rtsOff;
|
|
g_dbBase = g_mmioBase + dbOff;
|
|
|
|
KernelLogStream(INFO, "xHCI") << "MaxSlots: " << base::dec << (uint64_t)g_maxSlots
|
|
<< ", MaxPorts: " << (uint64_t)g_maxPorts
|
|
<< ", ScratchpadBufs: " << (uint64_t)maxScratchpadBufs;
|
|
|
|
// Cap slots to our maximum
|
|
if (g_maxSlots > MAX_SLOTS) {
|
|
g_maxSlots = MAX_SLOTS;
|
|
}
|
|
if (g_maxPorts > MAX_PORTS) {
|
|
g_maxPorts = MAX_PORTS;
|
|
}
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 5: Halt controller
|
|
// -----------------------------------------------------------------
|
|
uint32_t usbcmd = ReadOp(OP_USBCMD);
|
|
usbcmd &= ~USBCMD_RS;
|
|
WriteOp(OP_USBCMD, usbcmd);
|
|
|
|
// Wait for HCH (Halted) to be set
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (ReadOp(OP_USBSTS) & USBSTS_HCH) {
|
|
break;
|
|
}
|
|
for (int j = 0; j < 10; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_HCH)) {
|
|
KernelLogStream(WARNING, "xHCI") << "Controller failed to halt";
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Controller halted";
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 6: Reset controller
|
|
// -----------------------------------------------------------------
|
|
WriteOp(OP_USBCMD, USBCMD_HCRST);
|
|
|
|
// Wait for HCRST to clear
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBCMD) & USBCMD_HCRST)) {
|
|
break;
|
|
}
|
|
for (int j = 0; j < 10; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
// Wait for CNR (Controller Not Ready) to clear
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_CNR)) {
|
|
break;
|
|
}
|
|
for (int j = 0; j < 10; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
if (ReadOp(OP_USBSTS) & USBSTS_CNR) {
|
|
KernelLogStream(WARNING, "xHCI") << "Controller not ready after reset";
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Controller reset complete";
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 7: Program CONFIG register (MaxSlotsEn)
|
|
// -----------------------------------------------------------------
|
|
WriteOp(OP_CONFIG, g_maxSlots);
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 8: Allocate DCBAA
|
|
// -----------------------------------------------------------------
|
|
g_dcbaa = (uint64_t*)AllocateDmaBuffer(g_dcbaaPhys);
|
|
|
|
// Write DCBAAP (64-bit, split into two 32-bit writes)
|
|
WriteOp(OP_DCBAAP, (uint32_t)(g_dcbaaPhys & 0xFFFFFFFF));
|
|
WriteOp(OP_DCBAAP + 4, (uint32_t)(g_dcbaaPhys >> 32));
|
|
|
|
KernelLogStream(OK, "xHCI") << "DCBAA at phys " << base::hex << g_dcbaaPhys;
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 9: Scratchpad buffers
|
|
// -----------------------------------------------------------------
|
|
if (maxScratchpadBufs > 0) {
|
|
uint64_t spArrayPhys;
|
|
g_scratchpadBufs = (uint64_t*)AllocateDmaBuffer(spArrayPhys);
|
|
|
|
for (uint32_t i = 0; i < maxScratchpadBufs; i++) {
|
|
uint64_t bufPhys;
|
|
AllocateDmaBuffer(bufPhys);
|
|
g_scratchpadBufs[i] = bufPhys;
|
|
}
|
|
|
|
// DCBAA[0] = physical address of the scratchpad buffer array
|
|
g_dcbaa[0] = spArrayPhys;
|
|
|
|
KernelLogStream(OK, "xHCI") << "Allocated " << base::dec << (uint64_t)maxScratchpadBufs << " scratchpad buffers";
|
|
}
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 10: Command ring
|
|
// -----------------------------------------------------------------
|
|
g_cmdRing = (TRB*)AllocateDmaBuffer(g_cmdRingPhys);
|
|
|
|
// Set up Link TRB at the last position
|
|
TRB& linkTrb = g_cmdRing[CMD_RING_SIZE - 1];
|
|
linkTrb.Parameter0 = (uint32_t)(g_cmdRingPhys & 0xFFFFFFFF);
|
|
linkTrb.Parameter1 = (uint32_t)(g_cmdRingPhys >> 32);
|
|
linkTrb.Status = 0;
|
|
linkTrb.Control = (TRB_LINK << TRB_TYPE_SHIFT) | TRB_ENT;
|
|
// Toggle Cycle bit is bit 1 in the Link TRB control - use TRB_ENT which is bit 1
|
|
|
|
// Write CRCR = command ring physical address | cycle bit 1
|
|
uint64_t crcr = g_cmdRingPhys | TRB_CYCLE_BIT;
|
|
WriteOp(OP_CRCR, (uint32_t)(crcr & 0xFFFFFFFF));
|
|
WriteOp(OP_CRCR + 4, (uint32_t)(crcr >> 32));
|
|
|
|
g_cmdRingCCS = true;
|
|
g_cmdRingEnqueue = 0;
|
|
|
|
KernelLogStream(OK, "xHCI") << "Command ring at phys " << base::hex << g_cmdRingPhys;
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 11: Event ring + ERST
|
|
// -----------------------------------------------------------------
|
|
g_evtRing = (TRB*)AllocateDmaBuffer(g_evtRingPhys);
|
|
g_erst = (ERSTEntry*)AllocateDmaBuffer(g_erstPhys);
|
|
|
|
// Set up ERST entry 0
|
|
g_erst[0].RingSegmentBase = g_evtRingPhys;
|
|
g_erst[0].RingSegmentSize = EVT_RING_SIZE;
|
|
g_erst[0].Reserved = 0;
|
|
|
|
// Write interrupter 0 registers
|
|
// Order: ERSTSZ → ERDP → ERSTBA (ERSTBA triggers hardware read of ERST)
|
|
WriteRt(IR0_ERSTSZ, 1);
|
|
|
|
WriteRt(IR0_ERDP, (uint32_t)(g_evtRingPhys & 0xFFFFFFFF));
|
|
WriteRt(IR0_ERDP + 4, (uint32_t)(g_evtRingPhys >> 32));
|
|
|
|
// Write ERSTBA last (triggers hardware to read the ERST)
|
|
WriteRt(IR0_ERSTBA, (uint32_t)(g_erstPhys & 0xFFFFFFFF));
|
|
WriteRt(IR0_ERSTBA + 4, (uint32_t)(g_erstPhys >> 32));
|
|
|
|
g_evtRingCCS = true;
|
|
g_evtRingDequeue = 0;
|
|
|
|
KernelLogStream(OK, "xHCI") << "Event ring at phys " << base::hex << g_evtRingPhys;
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 12: MSI setup
|
|
// -----------------------------------------------------------------
|
|
if (!SetupMsi(foundDev->Bus, foundDev->Device, foundDev->Function)) {
|
|
KernelLogStream(WARNING, "xHCI") << "MSI not available, using poll mode";
|
|
}
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 13: Enable interrupter 0
|
|
// -----------------------------------------------------------------
|
|
WriteRt(IR0_IMAN, IMAN_IE);
|
|
WriteRt(IR0_IMOD, IMOD_INTERVAL_100US);
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 14: Start controller
|
|
// -----------------------------------------------------------------
|
|
WriteOp(OP_USBCMD, USBCMD_RS | USBCMD_INTE | USBCMD_HSEE);
|
|
|
|
// Wait for controller to start (HCH should clear)
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
if (!(ReadOp(OP_USBSTS) & USBSTS_HCH)) {
|
|
break;
|
|
}
|
|
for (int j = 0; j < 10; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Controller started";
|
|
|
|
g_initialized = true;
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 14.5: Power on all ports
|
|
// -----------------------------------------------------------------
|
|
for (uint32_t port = 0; port < g_maxPorts; port++) {
|
|
uint32_t portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (!(portsc & PORTSC_PP)) {
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE, PORTSC_PP);
|
|
}
|
|
}
|
|
// Wait for port power to stabilize (~20ms)
|
|
BusyWaitMs(20);
|
|
KernelLogStream(OK, "xHCI") << "All ports powered";
|
|
|
|
// -----------------------------------------------------------------
|
|
// Step 15: Port scanning
|
|
// -----------------------------------------------------------------
|
|
for (uint32_t port = 0; port < g_maxPorts; port++) {
|
|
uint32_t portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
|
|
// Check if device is connected (CCS)
|
|
if (!(portsc & PORTSC_CCS)) {
|
|
continue;
|
|
}
|
|
|
|
KernelLogStream(INFO, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1)
|
|
<< ": device connected, PORTSC=" << base::hex << (uint64_t)portsc;
|
|
|
|
// Reset the port: preserve power, clear change bits, set port reset
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_PR | PORTSC_CHANGE_BITS);
|
|
|
|
// Wait for Port Reset Change (PRC) to be set
|
|
bool resetDone = false;
|
|
for (uint32_t i = 0; i < 100000; i++) {
|
|
PollEvents();
|
|
uint32_t ps = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
if (ps & PORTSC_PRC) {
|
|
resetDone = true;
|
|
break;
|
|
}
|
|
for (int j = 0; j < 100; j++) {
|
|
asm volatile("" ::: "memory");
|
|
}
|
|
}
|
|
|
|
if (!resetDone) {
|
|
KernelLogStream(WARNING, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1) << " reset timeout";
|
|
continue;
|
|
}
|
|
|
|
// Re-read PORTSC after reset
|
|
portsc = ReadOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE);
|
|
uint32_t speed = (portsc >> 10) & 0xF;
|
|
|
|
// Clear change bits
|
|
WriteOp(OP_PORTSC_BASE + port * OP_PORTSC_STRIDE,
|
|
(portsc & PORTSC_PRESERVE) | PORTSC_CHANGE_BITS);
|
|
|
|
const char* speedStr = "Unknown";
|
|
switch (speed) {
|
|
case SPEED_FULL: speedStr = "Full (12 Mbps)"; break;
|
|
case SPEED_LOW: speedStr = "Low (1.5 Mbps)"; break;
|
|
case SPEED_HIGH: speedStr = "High (480 Mbps)"; break;
|
|
case SPEED_SUPER: speedStr = "Super (5 Gbps)"; break;
|
|
}
|
|
|
|
KernelLogStream(OK, "xHCI") << "Port " << base::dec << (uint64_t)(port + 1)
|
|
<< ": reset complete, speed=" << speedStr;
|
|
|
|
// Post-reset recovery delay (USB spec requires >= 10ms)
|
|
BusyWaitMs(10);
|
|
|
|
// Enumerate the device (port IDs are 1-based)
|
|
UsbDevice::EnumerateDevice(port + 1, speed);
|
|
}
|
|
|
|
g_bootScanComplete = true;
|
|
KernelLogStream(OK, "xHCI") << "Initialization complete";
|
|
}
|
|
|
|
};
|