60 lines
2.2 KiB
C++
60 lines
2.2 KiB
C++
/*
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* MSR.hpp
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* Model-Specific Register read/write helpers
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* Copyright (c) 2025 Daniel Hammer
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*/
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#pragma once
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#include <cstdint>
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namespace Hal {
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inline uint64_t ReadMSR(uint32_t msr) {
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uint32_t lo, hi;
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asm volatile("rdmsr" : "=a"(lo), "=d"(hi) : "c"(msr));
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return ((uint64_t)hi << 32) | lo;
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}
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inline void WriteMSR(uint32_t msr, uint64_t value) {
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uint32_t lo = (uint32_t)(value & 0xFFFFFFFF);
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uint32_t hi = (uint32_t)(value >> 32);
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asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
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}
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// Well-known MSR addresses
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static constexpr uint32_t IA32_EFER = 0xC0000080;
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static constexpr uint32_t IA32_STAR = 0xC0000081;
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static constexpr uint32_t IA32_LSTAR = 0xC0000082;
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static constexpr uint32_t IA32_FMASK = 0xC0000084;
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static constexpr uint32_t IA32_PAT = 0x00000277;
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// PAT memory type encodings
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static constexpr uint8_t PAT_UC = 0x00; // Uncacheable
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static constexpr uint8_t PAT_WC = 0x01; // Write Combining
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static constexpr uint8_t PAT_WT = 0x04; // Write Through
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static constexpr uint8_t PAT_WP = 0x05; // Write Protect
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static constexpr uint8_t PAT_WB = 0x06; // Write Back
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static constexpr uint8_t PAT_UCM = 0x07; // UC- (UC minus)
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// Program PAT so entry 1 = WC (default is WT).
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// PAT index is selected by PTE bits: PAT(bit7) | PCD(bit4) | PWT(bit3)
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// Entry 0 (000) = WB — normal memory (unchanged)
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// Entry 1 (001) = WC — framebuffers (was WT)
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// Entry 2 (010) = UC- — (unchanged)
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// Entry 3 (011) = UC — MMIO registers (unchanged)
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// Entries 4-7: unchanged from defaults
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inline void InitializePAT() {
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uint64_t pat =
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((uint64_t)PAT_WB << 0) | // Entry 0: WB
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((uint64_t)PAT_WC << 8) | // Entry 1: WC (was WT)
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((uint64_t)PAT_UCM << 16) | // Entry 2: UC-
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((uint64_t)PAT_UC << 24) | // Entry 3: UC
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((uint64_t)PAT_WB << 32) | // Entry 4: WB
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((uint64_t)PAT_WT << 40) | // Entry 5: WT
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((uint64_t)PAT_UCM << 48) | // Entry 6: UC-
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((uint64_t)PAT_UC << 56); // Entry 7: UC
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WriteMSR(IA32_PAT, pat);
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}
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}
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