feat: Intel GPU fixes, add tcc compiler, spreadsheet improvements, paint app, file manager improvements
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@@ -107,15 +107,36 @@ namespace Drivers::Graphics::IntelGPU {
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<< " at PCI " << (uint64_t)found->Bus << ":"
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<< (uint64_t)found->Device << "." << (uint64_t)found->Function;
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} else {
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// Unknown device ID - accept generically but warn
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g_gpuInfo.gen = 7; // Assume gen 7 as a safe default
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// Unknown device ID - infer generation from device ID range.
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// Getting this wrong is catastrophic (32-bit vs 64-bit GTT PTEs),
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// so use known Intel device ID patterns.
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uint16_t did = found->DeviceId;
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uint8_t inferredGen;
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if (did >= 0xA700 || (did >= 0x4600 && did < 0x4700) ||
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(did >= 0x5600 && did < 0x5700) || (did >= 0x7D00 && did < 0x7E00)) {
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inferredGen = 12; // Raptor Lake, Alder Lake, DG2, Meteor Lake range
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} else if ((did >= 0x8A00 && did < 0x8B00) ||
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(did >= 0x9A00 && did < 0x9B00)) {
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inferredGen = 12; // Ice Lake / Tiger Lake range
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} else if ((did >= 0x3E00 && did < 0x3F00) ||
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(did >= 0x5900 && did < 0x5A00) ||
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(did >= 0x9B00 && did < 0x9C00) ||
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(did >= 0x1900 && did < 0x1A00)) {
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inferredGen = 9; // Skylake / Kaby Lake / Coffee Lake / Comet Lake
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} else if (did >= 0x1600 && did < 0x1700) {
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inferredGen = 8; // Broadwell
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} else {
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inferredGen = 7; // Older (Haswell and below)
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}
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g_gpuInfo.gen = inferredGen;
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g_gpuInfo.name = "Intel GPU";
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KernelLogStream(WARNING, "IntelGPU") << "Unknown Intel display controller "
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<< "(device " << base::hex << (uint64_t)found->DeviceId << ")"
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<< " at PCI " << (uint64_t)found->Bus << ":"
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<< (uint64_t)found->Device << "." << (uint64_t)found->Function
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<< " - attempting generic initialization";
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<< " - inferred gen " << base::dec << (uint64_t)inferredGen
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<< ", attempting generic initialization";
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}
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g_gpuGen = g_gpuInfo.gen;
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@@ -494,13 +515,32 @@ namespace Drivers::Graphics::IntelGPU {
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<< " at PCI " << (uint64_t)dev.Bus << ":"
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<< (uint64_t)dev.Device << "." << (uint64_t)dev.Function;
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} else {
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g_gpuInfo.gen = 7;
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uint16_t did = dev.DeviceId;
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uint8_t inferredGen;
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if (did >= 0xA700 || (did >= 0x4600 && did < 0x4700) ||
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(did >= 0x5600 && did < 0x5700) || (did >= 0x7D00 && did < 0x7E00)) {
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inferredGen = 12;
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} else if ((did >= 0x8A00 && did < 0x8B00) ||
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(did >= 0x9A00 && did < 0x9B00)) {
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inferredGen = 12;
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} else if ((did >= 0x3E00 && did < 0x3F00) ||
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(did >= 0x5900 && did < 0x5A00) ||
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(did >= 0x9B00 && did < 0x9C00) ||
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(did >= 0x1900 && did < 0x1A00)) {
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inferredGen = 9;
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} else if (did >= 0x1600 && did < 0x1700) {
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inferredGen = 8;
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} else {
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inferredGen = 7;
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}
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g_gpuInfo.gen = inferredGen;
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g_gpuInfo.name = "Intel GPU";
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KernelLogStream(WARNING, "IntelGPU") << "Unknown Intel display controller "
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<< "(device " << base::hex << (uint64_t)dev.DeviceId << ")"
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<< " at PCI " << (uint64_t)dev.Bus << ":"
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<< (uint64_t)dev.Device << "." << (uint64_t)dev.Function
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<< " - attempting generic initialization";
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<< " - inferred gen " << base::dec << (uint64_t)inferredGen
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<< ", attempting generic initialization";
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}
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g_gpuGen = g_gpuInfo.gen;
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@@ -643,14 +683,35 @@ namespace Drivers::Graphics::IntelGPU {
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void Reinitialize() {
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if (!g_initialized || !g_mmioBase) return;
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KernelLogStream(INFO, "IntelGPU") << "Reinitializing display after S3 resume";
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KernelLogStream(INFO, "IntelGPU") << "Reinitializing display after S3 resume"
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<< " (gen " << base::dec << (uint64_t)g_gpuGen << ")";
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// 1. Re-enable PCI memory space and bus mastering. S3 resets the PCI
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// command register, so MMIO writes to the GPU are silently dropped
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// until we re-enable these bits.
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Pci::EnableBusMaster(g_gpuInfo.pciBus, g_gpuInfo.pciDevice, g_gpuInfo.pciFunction);
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KernelLogStream(DEBUG, "IntelGPU") << "PCI memory space and bus mastering re-enabled";
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// Verify PCI memory space is accessible by reading back command register
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uint16_t pciCmd = Pci::LegacyRead16(g_gpuInfo.pciBus, g_gpuInfo.pciDevice,
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g_gpuInfo.pciFunction, (uint8_t)Pci::PCI_REG_COMMAND);
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if (!(pciCmd & Pci::PCI_CMD_MEM_SPACE)) {
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KernelLogStream(ERROR, "IntelGPU")
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<< "PCI memory space not enabled after restore (cmd="
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<< base::hex << (uint64_t)pciCmd << ")";
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return;
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}
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// Sanity-check MMIO access: read a register and verify we don't get 0xFFFFFFFF
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// (which indicates the device is not responding on the PCI bus)
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uint32_t testRead = ReadReg(PIPEACONF);
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if (testRead == 0xFFFFFFFF) {
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KernelLogStream(ERROR, "IntelGPU")
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<< "MMIO reads return 0xFFFFFFFF - GPU not responding";
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return;
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}
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KernelLogStream(DEBUG, "IntelGPU") << "PCI memory space verified (cmd="
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<< base::hex << (uint64_t)pciCmd << ")";
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// 2. Disable VGA plane (firmware may have re-enabled it during POST)
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DisableVga();
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@@ -673,6 +734,9 @@ namespace Drivers::Graphics::IntelGPU {
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(void)gtt32[pageCount - 1];
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}
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KernelLogStream(DEBUG, "IntelGPU") << "GTT reprogrammed: " << base::dec << pageCount
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<< " pages (" << (g_gpuGen >= 8 ? "64-bit" : "32-bit") << " PTEs)";
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// 4. Re-enable the display pipe. After S3, the pipe may be off even
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// though the firmware lit the backlight. Wait for it to become
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// active before programming the display plane.
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@@ -686,6 +750,11 @@ namespace Drivers::Graphics::IntelGPU {
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break;
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asm volatile("pause");
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}
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if (!(ReadReg(PIPEACONF) & PIPECONF_STATE)) {
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KernelLogStream(WARNING, "IntelGPU")
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<< "Pipe A did not become active after enable";
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}
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}
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// 5. Reprogram display plane to point at our GTT-mapped framebuffer
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@@ -111,6 +111,22 @@ namespace Drivers::Graphics::IntelGPU {
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{0x4680, 12, "Alder Lake-S GT1"},
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{0x4692, 12, "Alder Lake-S GT1"},
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{0x46A6, 12, "Alder Lake-P GT2"},
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// Gen 12 - Raptor Lake-P
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{0xA7A0, 12, "Raptor Lake-P GT2"},
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{0xA7A1, 12, "Raptor Lake-P GT2"},
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{0xA720, 12, "Raptor Lake-P GT2"},
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{0xA721, 12, "Raptor Lake-P GT2"},
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{0xA7A8, 12, "Raptor Lake-P GT2"},
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{0xA7A9, 12, "Raptor Lake-P GT2"},
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// Gen 12 - Raptor Lake-S
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{0xA780, 12, "Raptor Lake-S GT1"},
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{0xA781, 12, "Raptor Lake-S GT1"},
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{0xA782, 12, "Raptor Lake-S GT2"},
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{0xA783, 12, "Raptor Lake-S GT2"},
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{0xA788, 12, "Raptor Lake-S GT1"},
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{0xA789, 12, "Raptor Lake-S GT1"},
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};
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static constexpr int SupportedDeviceCount = sizeof(SupportedDevices) / sizeof(SupportedDevices[0]);
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