feat: Intel HDA audio driver, audio streaming syscalls, userspace Music app, fixes and improvements, rudimentary Bluetooth support
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/*
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* IntelHda.hpp
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* Intel High Definition Audio controller driver
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* Copyright (c) 2026 Daniel Hammer
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*/
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#pragma once
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#include <cstdint>
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#include <Pci/Pci.hpp>
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namespace Drivers::Audio::IntelHda {
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// =========================================================================
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// HDA controller registers (memory-mapped via BAR0)
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// Ref: Intel High Definition Audio Specification, Rev 1.0a
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// =========================================================================
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// Global registers
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constexpr uint32_t REG_GCAP = 0x00; // Global Capabilities (16-bit)
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constexpr uint32_t REG_VMIN = 0x02; // Minor Version (8-bit)
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constexpr uint32_t REG_VMAJ = 0x03; // Major Version (8-bit)
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constexpr uint32_t REG_OUTPAY = 0x04; // Output Payload Capability (16-bit)
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constexpr uint32_t REG_INPAY = 0x06; // Input Payload Capability (16-bit)
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constexpr uint32_t REG_GCTL = 0x08; // Global Control (32-bit)
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constexpr uint32_t REG_WAKEEN = 0x0C; // Wake Enable (16-bit)
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constexpr uint32_t REG_STATESTS = 0x0E; // State Change Status (16-bit)
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constexpr uint32_t REG_GSTS = 0x10; // Global Status (16-bit)
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constexpr uint32_t REG_INTCTL = 0x20; // Interrupt Control (32-bit)
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constexpr uint32_t REG_INTSTS = 0x24; // Interrupt Status (32-bit)
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constexpr uint32_t REG_WALCLK = 0x30; // Wall Clock Counter (32-bit)
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constexpr uint32_t REG_SSYNC = 0x38; // Stream Synchronization (32-bit)
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// CORB registers
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constexpr uint32_t REG_CORBLBASE = 0x40; // CORB Lower Base Address (32-bit)
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constexpr uint32_t REG_CORBUBASE = 0x44; // CORB Upper Base Address (32-bit)
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constexpr uint32_t REG_CORBWP = 0x48; // CORB Write Pointer (16-bit)
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constexpr uint32_t REG_CORBRP = 0x4A; // CORB Read Pointer (16-bit)
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constexpr uint32_t REG_CORBCTL = 0x4C; // CORB Control (8-bit)
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constexpr uint32_t REG_CORBSTS = 0x4D; // CORB Status (8-bit)
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constexpr uint32_t REG_CORBSIZE = 0x4E; // CORB Size (8-bit)
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// RIRB registers
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constexpr uint32_t REG_RIRBLBASE = 0x50; // RIRB Lower Base Address (32-bit)
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constexpr uint32_t REG_RIRBUBASE = 0x54; // RIRB Upper Base Address (32-bit)
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constexpr uint32_t REG_RIRBWP = 0x58; // RIRB Write Pointer (16-bit)
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constexpr uint32_t REG_RINTCNT = 0x5A; // Response Interrupt Count (16-bit)
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constexpr uint32_t REG_RIRBCTL = 0x5C; // RIRB Control (8-bit)
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constexpr uint32_t REG_RIRBSTS = 0x5D; // RIRB Status (8-bit)
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constexpr uint32_t REG_RIRBSIZE = 0x5E; // RIRB Size (8-bit)
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// Immediate command interface
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constexpr uint32_t REG_ICW = 0x60; // Immediate Command Write (32-bit)
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constexpr uint32_t REG_IRR = 0x64; // Immediate Response Read (32-bit)
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constexpr uint32_t REG_ICS = 0x68; // Immediate Command Status (16-bit)
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// DMA Position Buffer
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constexpr uint32_t REG_DPIBLBASE = 0x70; // DMA Position Lower Base (32-bit)
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constexpr uint32_t REG_DPIBUBASE = 0x74; // DMA Position Upper Base (32-bit)
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// GCTL register bits
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constexpr uint32_t GCTL_CRST = (1u << 0); // Controller Reset
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constexpr uint32_t GCTL_FCNTRL = (1u << 1); // Flush Control
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constexpr uint32_t GCTL_UNSOL = (1u << 8); // Accept Unsolicited Responses
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// INTCTL register bits
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constexpr uint32_t INTCTL_GIE = (1u << 31); // Global Interrupt Enable
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constexpr uint32_t INTCTL_CIE = (1u << 30); // Controller Interrupt Enable
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// CORBCTL register bits
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constexpr uint8_t CORBCTL_RUN = (1u << 1); // CORB DMA Engine Run
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constexpr uint8_t CORBCTL_MEIE = (1u << 0); // Memory Error Interrupt Enable
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// RIRBCTL register bits
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constexpr uint8_t RIRBCTL_RUN = (1u << 1); // RIRB DMA Engine Run
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constexpr uint8_t RIRBCTL_RINTCTL = (1u << 0); // Response Interrupt Control
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// RIRBSTS register bits
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constexpr uint8_t RIRBSTS_RINTFL = (1u << 0); // Response Interrupt
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// CORBRP register bits
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constexpr uint16_t CORBRP_RST = (1u << 15); // CORB Read Pointer Reset
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// RIRBWP register bits
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constexpr uint16_t RIRBWP_RST = (1u << 15); // RIRB Write Pointer Reset
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// =========================================================================
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// Stream Descriptor registers (offset = 0x80 + streamIndex * 0x20)
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// =========================================================================
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constexpr uint32_t SD_BASE = 0x80;
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constexpr uint32_t SD_SIZE = 0x20;
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// Stream descriptor register offsets (relative to stream base)
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constexpr uint32_t SD_CTL = 0x00; // Control (24-bit: bytes 0,1,2)
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constexpr uint32_t SD_STS = 0x03; // Status (8-bit)
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constexpr uint32_t SD_LPIB = 0x04; // Link Position in Current Buffer (32-bit)
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constexpr uint32_t SD_CBL = 0x08; // Cyclic Buffer Length (32-bit)
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constexpr uint32_t SD_LVI = 0x0C; // Last Valid Index (16-bit)
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constexpr uint32_t SD_FIFOS = 0x10; // FIFO Size (16-bit, read-only)
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constexpr uint32_t SD_FMT = 0x12; // Format (16-bit)
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constexpr uint32_t SD_BDPL = 0x18; // BDL Pointer Lower (32-bit)
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constexpr uint32_t SD_BDPU = 0x1C; // BDL Pointer Upper (32-bit)
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// Stream control bits (CTL is 24-bit, accessed as 3 bytes)
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constexpr uint8_t SD_CTL0_SRST = (1u << 0); // Stream Reset
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constexpr uint8_t SD_CTL0_RUN = (1u << 1); // Stream Run
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constexpr uint8_t SD_CTL0_IOCE = (1u << 2); // Interrupt On Completion Enable
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constexpr uint8_t SD_CTL0_FEIE = (1u << 3); // FIFO Error Interrupt Enable
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constexpr uint8_t SD_CTL0_DEIE = (1u << 4); // Descriptor Error Interrupt Enable
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// CTL byte 2 (offset +2): bits 23:20 = Stream Number (1-15)
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// Stream status bits
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constexpr uint8_t SD_STS_BCIS = (1u << 2); // Buffer Completion Interrupt Status
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constexpr uint8_t SD_STS_FIFOE = (1u << 3); // FIFO Error
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constexpr uint8_t SD_STS_DESE = (1u << 4); // Descriptor Error
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// =========================================================================
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// Stream format register encoding (SD_FMT, 16-bit)
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// =========================================================================
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// Bit 15: Stream Type (0=PCM, 1=non-PCM)
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// Bits 14: Base Rate (0=48kHz, 1=44.1kHz)
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// Bits 13:11: Sample Rate Multiplier (0=x1, 1=x2, 2=x3, 3=x4)
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// Bits 10:8: Sample Rate Divisor (0=/1, 1=/2, 2=/3, ..., 7=/8)
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// Bits 7:4: Bits Per Sample (000=8, 001=16, 010=20, 011=24, 100=32)
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// Bits 3:0: Number of Channels - 1
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constexpr uint16_t FMT_BASE_44K = (1u << 14);
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constexpr uint16_t FMT_BASE_48K = 0;
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// =========================================================================
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// Buffer Descriptor List Entry (16 bytes)
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// =========================================================================
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struct BdlEntry {
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uint64_t Address; // Physical address of buffer
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uint32_t Length; // Length in bytes
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uint32_t Ioc; // Bit 0: Interrupt on Completion
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} __attribute__((packed));
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static_assert(sizeof(BdlEntry) == 16, "BDL entry must be 16 bytes");
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// =========================================================================
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// RIRB response entry (8 bytes)
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// =========================================================================
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struct RirbEntry {
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uint32_t Response;
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uint32_t ResponseEx; // Bits 3:0 = Codec Address, Bit 4 = Unsolicited
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} __attribute__((packed));
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static_assert(sizeof(RirbEntry) == 8, "RIRB entry must be 8 bytes");
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// =========================================================================
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// HDA Codec verbs
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// =========================================================================
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// Verb construction: (codec << 28) | (nid << 20) | verb
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// Get Parameter: verb = 0xF0000 | paramId
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// Set Converter Format: verb = 0x20000 | format
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// Set Amp Gain/Mute: verb = 0x30000 | payload
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// Set Converter Stream/Channel: verb = 0x70600 | (stream << 4) | channel
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// Set Pin Widget Control: verb = 0x70700 | value
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// Set EAPD/BTL Enable: verb = 0x70C00 | value
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// Set Power State: verb = 0x70500 | state
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// Get Config Default: verb = 0xF1C00
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// Set Connection Select: verb = 0x70100 | index
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// Parameter IDs
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constexpr uint32_t PARAM_VENDOR_ID = 0x00;
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constexpr uint32_t PARAM_REVISION_ID = 0x02;
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constexpr uint32_t PARAM_SUB_NODE_COUNT = 0x04;
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constexpr uint32_t PARAM_FN_GROUP_TYPE = 0x05;
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constexpr uint32_t PARAM_AUDIO_WIDGET_CAP = 0x09;
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constexpr uint32_t PARAM_PCM_RATES = 0x0A;
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constexpr uint32_t PARAM_STREAM_FORMATS = 0x0B;
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constexpr uint32_t PARAM_PIN_CAPS = 0x0C;
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constexpr uint32_t PARAM_INPUT_AMP_CAP = 0x0D;
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constexpr uint32_t PARAM_CONN_LIST_LEN = 0x0E;
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constexpr uint32_t PARAM_POWER_STATES = 0x0F;
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constexpr uint32_t PARAM_OUTPUT_AMP_CAP = 0x12;
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// Widget types (bits 23:20 of Audio Widget Capabilities)
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constexpr uint8_t WIDGET_AUDIO_OUTPUT = 0x0;
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constexpr uint8_t WIDGET_AUDIO_INPUT = 0x1;
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constexpr uint8_t WIDGET_AUDIO_MIXER = 0x2;
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constexpr uint8_t WIDGET_AUDIO_SELECTOR = 0x3;
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constexpr uint8_t WIDGET_PIN_COMPLEX = 0x4;
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constexpr uint8_t WIDGET_POWER = 0x5;
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constexpr uint8_t WIDGET_VOLUME_KNOB = 0x6;
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constexpr uint8_t WIDGET_BEEP_GEN = 0x7;
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constexpr uint8_t WIDGET_VENDOR_DEFINED = 0xF;
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// Pin default config: device type (bits 23:20)
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constexpr uint8_t PIN_DEV_LINE_OUT = 0x0;
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constexpr uint8_t PIN_DEV_SPEAKER = 0x1;
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constexpr uint8_t PIN_DEV_HP_OUT = 0x2;
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constexpr uint8_t PIN_DEV_CD = 0x3;
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constexpr uint8_t PIN_DEV_SPDIF_OUT = 0x4;
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constexpr uint8_t PIN_DEV_LINE_IN = 0x8;
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constexpr uint8_t PIN_DEV_MIC_IN = 0xA;
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// Pin widget control bits
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constexpr uint8_t PIN_CTL_ENABLE_OUTPUT = (1u << 6); // OUT Enable
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constexpr uint8_t PIN_CTL_ENABLE_INPUT = (1u << 5); // IN Enable
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constexpr uint8_t PIN_CTL_ENABLE_HP = (1u << 7); // Headphone enable
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// EAPD/BTL bits
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constexpr uint8_t EAPD_ENABLE = (1u << 1);
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// Amp gain/mute verb payload bits
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constexpr uint16_t AMP_SET_OUTPUT = (1u << 15);
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constexpr uint16_t AMP_SET_INPUT = (1u << 14);
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constexpr uint16_t AMP_SET_LEFT = (1u << 13);
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constexpr uint16_t AMP_SET_RIGHT = (1u << 12);
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constexpr uint16_t AMP_MUTE = (1u << 7);
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// =========================================================================
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// Ring buffer sizes
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// =========================================================================
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constexpr int CORB_ENTRIES = 256; // 256 entries * 4 bytes = 1024 bytes
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constexpr int RIRB_ENTRIES = 256; // 256 entries * 8 bytes = 2048 bytes
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constexpr int BDL_MAX_ENTRIES = 256; // Max BDL entries per stream
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// =========================================================================
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// DMA buffer configuration
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// =========================================================================
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constexpr int BUFFER_COUNT = 2; // Double-buffered
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constexpr int BUFFER_SIZE = 0x4000; // 16 KiB per buffer segment
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constexpr int TOTAL_BUFFER_SIZE = BUFFER_COUNT * BUFFER_SIZE;
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// =========================================================================
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// MSI configuration
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// =========================================================================
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constexpr uint8_t MSI_IRQ = 27; // IRQ slot 27 = vector 59
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constexpr uint32_t MSI_VECTOR = 59;
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constexpr uint32_t MSI_ADDR_BASE = 0xFEE00000;
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// =========================================================================
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// Audio stream state (one active output stream)
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// =========================================================================
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struct AudioStream {
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bool Active;
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uint32_t SampleRate;
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uint8_t Channels;
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uint8_t BitsPerSample;
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uint8_t StreamIndex; // HDA stream index
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uint8_t StreamTag; // HDA stream tag (1-15)
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volatile uint32_t WritePos; // Write position in ring buffer (bytes)
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};
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// =========================================================================
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// Public API
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// =========================================================================
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bool Probe(const Pci::PciDevice& dev);
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bool IsInitialized();
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// Returns the codec vendor/device ID (vendor in upper 16 bits, device in lower 16).
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// Returns 0 if no codec was found.
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uint32_t GetCodecVendorId();
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// Open an output stream. Returns stream handle (0) or -1 on failure.
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int Open(uint32_t sampleRate, uint8_t channels, uint8_t bitsPerSample);
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// Close an output stream.
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void Close(int handle);
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// Write PCM sample data to the stream buffer.
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// Returns number of bytes written (may be less than requested if buffer full).
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int Write(int handle, const uint8_t* data, uint32_t size);
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// Control commands
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constexpr int AUDIO_CTL_SET_VOLUME = 0; // value: 0-100
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constexpr int AUDIO_CTL_GET_VOLUME = 1;
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constexpr int AUDIO_CTL_GET_POS = 2; // returns playback position in bytes
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constexpr int AUDIO_CTL_PAUSE = 3; // value: 1=pause, 0=resume
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int Control(int handle, int cmd, int value);
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};
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