feat: expand Intel GPU display management
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daniel committed
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25 files changed
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@@ -61,6 +61,29 @@ namespace Drivers::Graphics::IntelGPU {
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static volatile uint64_t g_vblankCount = 0;
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static bool g_vblankIrqReady = false;
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// Modesetting/display-management state. The firmware-trained port and
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// link are deliberately retained; the driver owns the active transcoder,
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// timing catalogue, panel PWM, and validated timing transactions.
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static constexpr int MaxDisplayModes = 32;
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struct ModeRecord {
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DisplayMode timing;
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uint32_t refreshMilliHz;
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uint32_t flags;
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};
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static ModeRecord g_modes[MaxDisplayModes] = {};
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static int g_modeCount = 0;
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static int g_currentMode = -1;
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static uint32_t g_transTimingBase = TRANS_TIMING_A;
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static uint32_t g_transConfReg = TRANS_CONF_A;
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static uint32_t g_transDdiReg = TRANS_DDI_A;
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static uint8_t g_connectorType = montauk::abi::DISPLAY_CONNECTOR_UNKNOWN;
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static bool g_connectorConnected = false;
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static bool g_edidValid = false;
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static bool g_pwmSupported = false;
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static uint32_t g_pwmCtlReg = 0;
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static char g_connectorName[32] = "Unknown";
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static char g_monitorName[64] = "Unknown display";
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// =========================================================================
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// Register access helpers
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// =========================================================================
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@@ -73,6 +96,33 @@ namespace Drivers::Graphics::IntelGPU {
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return *(volatile uint32_t*)(g_mmioBase + reg);
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}
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static void CopyText(char* dst, uint64_t cap, const char* src) {
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if (!dst || cap == 0) return;
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uint64_t i = 0;
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if (src) {
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while (i + 1 < cap && src[i]) {
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dst[i] = src[i];
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i++;
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}
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}
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dst[i] = '\0';
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}
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static void CopyEdidText(char* dst, uint64_t cap, const uint8_t* src, int len) {
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if (!dst || cap == 0) return;
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int end = len;
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while (end > 0 && (src[end - 1] == ' ' || src[end - 1] == '\n'
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|| src[end - 1] == '\r' || src[end - 1] == '\0')) {
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end--;
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}
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uint64_t out = 0;
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for (int i = 0; i < end && out + 1 < cap; i++) {
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uint8_t ch = src[i];
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dst[out++] = (ch >= 0x20 && ch <= 0x7e) ? (char)ch : '?';
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}
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dst[out] = '\0';
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}
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// =========================================================================
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// PCI Detection
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// =========================================================================
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@@ -317,6 +367,350 @@ namespace Drivers::Graphics::IntelGPU {
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return true;
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}
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// =========================================================================
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// Connector discovery, EDID, and mode catalogue
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// =========================================================================
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static uint32_t ModeRefreshMilliHz(const DisplayMode& mode) {
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uint64_t pixels = (uint64_t)mode.htotal * mode.vtotal;
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if (pixels == 0 || mode.pixelClock == 0) return 0;
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return (uint32_t)(((uint64_t)mode.pixelClock * 1000000ULL + pixels / 2) / pixels);
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}
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static bool SameMode(const ModeRecord& a, const DisplayMode& mode,
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uint32_t refreshMilliHz) {
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if (a.timing.hdisplay != mode.hdisplay || a.timing.vdisplay != mode.vdisplay)
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return false;
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if (a.timing.htotal && mode.htotal
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&& (a.timing.htotal != mode.htotal || a.timing.vtotal != mode.vtotal))
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return false;
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uint32_t ar = a.refreshMilliHz;
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uint32_t diff = ar > refreshMilliHz ? ar - refreshMilliHz : refreshMilliHz - ar;
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return ar == 0 || refreshMilliHz == 0 || diff <= 500;
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}
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static int AddMode(const DisplayMode& mode, uint32_t refreshMilliHz,
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uint32_t flags) {
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if (mode.hdisplay < 320 || mode.vdisplay < 200
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|| mode.hdisplay > 16384 || mode.vdisplay > 16384)
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return -1;
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if (refreshMilliHz == 0) refreshMilliHz = ModeRefreshMilliHz(mode);
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for (int i = 0; i < g_modeCount; i++) {
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if (SameMode(g_modes[i], mode, refreshMilliHz)) {
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g_modes[i].flags |= flags;
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if (g_modes[i].timing.pixelClock == 0 && mode.pixelClock)
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g_modes[i].timing = mode;
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return i;
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}
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}
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if (g_modeCount >= MaxDisplayModes) return -1;
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int index = g_modeCount++;
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g_modes[index].timing = mode;
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g_modes[index].refreshMilliHz = refreshMilliHz;
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g_modes[index].flags = flags;
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return index;
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}
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static void AddSimpleMode(uint32_t width, uint32_t height, uint32_t refreshHz,
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uint32_t flags = 0) {
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DisplayMode mode = {};
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mode.hdisplay = width;
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mode.vdisplay = height;
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AddMode(mode, refreshHz * 1000, flags);
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}
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static bool EdidBlockValid(const uint8_t* block) {
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uint8_t sum = 0;
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for (int i = 0; i < 128; i++) sum = (uint8_t)(sum + block[i]);
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return sum == 0;
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}
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static bool ParseDetailedTiming(const uint8_t* dtd, DisplayMode& mode) {
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uint32_t clock10KHz = (uint32_t)dtd[0] | ((uint32_t)dtd[1] << 8);
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if (clock10KHz == 0) return false;
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uint32_t hactive = dtd[2] | ((uint32_t)(dtd[4] & 0xF0) << 4);
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uint32_t hblank = dtd[3] | ((uint32_t)(dtd[4] & 0x0F) << 8);
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uint32_t vactive = dtd[5] | ((uint32_t)(dtd[7] & 0xF0) << 4);
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uint32_t vblank = dtd[6] | ((uint32_t)(dtd[7] & 0x0F) << 8);
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uint32_t hsyncOffset = dtd[8] | ((uint32_t)(dtd[11] & 0xC0) << 2);
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uint32_t hsyncWidth = dtd[9] | ((uint32_t)(dtd[11] & 0x30) << 4);
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uint32_t vsyncOffset = ((dtd[10] >> 4) & 0x0F)
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| ((uint32_t)(dtd[11] & 0x0C) << 2);
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uint32_t vsyncWidth = (dtd[10] & 0x0F)
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| ((uint32_t)(dtd[11] & 0x03) << 4);
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if (!hactive || !vactive || !hblank || !vblank) return false;
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mode = {};
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mode.hdisplay = hactive;
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mode.hsyncStart = hactive + hsyncOffset;
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mode.hsyncEnd = mode.hsyncStart + hsyncWidth;
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mode.htotal = hactive + hblank;
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mode.vdisplay = vactive;
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mode.vsyncStart = vactive + vsyncOffset;
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mode.vsyncEnd = mode.vsyncStart + vsyncWidth;
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mode.vtotal = vactive + vblank;
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mode.pixelClock = clock10KHz * 10;
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mode.hsyncPositive = (dtd[17] & (1u << 1)) != 0;
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mode.vsyncPositive = (dtd[17] & (1u << 2)) != 0;
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return true;
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}
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static void ParseEdid() {
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uint64_t edidSize = 0;
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const uint8_t* edid = ::Graphics::Framebuffer::GetEdid(&edidSize);
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if (!edid || edidSize < 128) return;
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static constexpr uint8_t header[8] = {0x00, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0x00};
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if (memcmp(edid, header, sizeof(header)) != 0 || !EdidBlockValid(edid)) {
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KernelLogStream(WARNING, "IntelGPU") << "Boot EDID failed validation";
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return;
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}
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g_edidValid = true;
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// Established timings from EDID 1.3 section 3.8.
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if (edid[35] & 0x20) AddSimpleMode(640, 480, 60);
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if (edid[35] & 0x08) AddSimpleMode(640, 480, 72);
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if (edid[35] & 0x04) AddSimpleMode(640, 480, 75);
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if (edid[35] & 0x02) AddSimpleMode(800, 600, 56);
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if (edid[35] & 0x01) AddSimpleMode(800, 600, 60);
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if (edid[36] & 0x80) AddSimpleMode(800, 600, 72);
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if (edid[36] & 0x40) AddSimpleMode(800, 600, 75);
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if (edid[36] & 0x08) AddSimpleMode(1024, 768, 60);
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if (edid[36] & 0x04) AddSimpleMode(1024, 768, 70);
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if (edid[36] & 0x02) AddSimpleMode(1024, 768, 75);
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if (edid[36] & 0x01) AddSimpleMode(1280, 1024, 75);
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// Standard timings carry geometry and refresh but no porch/sync data.
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for (int off = 38; off < 54; off += 2) {
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if (edid[off] == 0x01 && edid[off + 1] == 0x01) continue;
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uint32_t width = ((uint32_t)edid[off] + 31) * 8;
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uint32_t aspect = (edid[off + 1] >> 6) & 3;
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uint32_t height = aspect == 0 ? width * 10 / 16
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: aspect == 1 ? width * 3 / 4
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: aspect == 2 ? width * 4 / 5
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: width * 9 / 16;
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AddSimpleMode(width, height, (edid[off + 1] & 0x3F) + 60);
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}
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// Base-block detailed timings and monitor name descriptor.
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bool firstDetailed = true;
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for (int off = 54; off + 18 <= 126; off += 18) {
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DisplayMode mode;
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if (ParseDetailedTiming(edid + off, mode)) {
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AddMode(mode, 0, firstDetailed ? montauk::abi::DISPLAY_MODE_PREFERRED : 0);
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firstDetailed = false;
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} else if (edid[off + 3] == 0xFC) {
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CopyEdidText(g_monitorName, sizeof(g_monitorName), edid + off + 5, 13);
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}
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}
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// CTA-861 extension detailed timings. Other extension types are kept
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// untouched; their mode encodings need format-specific parsers.
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uint32_t blocks = 1 + edid[126];
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if (blocks * 128 > edidSize) blocks = (uint32_t)(edidSize / 128);
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for (uint32_t block = 1; block < blocks; block++) {
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const uint8_t* ext = edid + block * 128;
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if (!EdidBlockValid(ext) || ext[0] != 0x02) continue;
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int start = ext[2];
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if (start == 0 || start < 4 || start > 126) continue;
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for (int off = start; off + 18 <= 127; off += 18) {
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DisplayMode mode;
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if (ParseDetailedTiming(ext + off, mode)) AddMode(mode, 0, 0);
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}
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}
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KernelLogStream(OK, "IntelGPU") << "EDID: " << g_monitorName
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<< ", " << base::dec << (uint64_t)g_modeCount << " modes";
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}
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struct TranscoderCandidate {
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uint32_t timing;
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uint32_t conf;
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uint32_t ddi;
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const char* name;
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bool edp;
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};
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static void DiscoverActiveTranscoder() {
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static constexpr TranscoderCandidate candidates[] = {
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{TRANS_TIMING_EDP, TRANS_CONF_EDP, TRANS_DDI_EDP, "eDP-1", true},
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{TRANS_TIMING_A, TRANS_CONF_A, TRANS_DDI_A, "Pipe A", false},
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{TRANS_TIMING_B, TRANS_CONF_B, TRANS_DDI_B, "Pipe B", false},
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{TRANS_TIMING_C, TRANS_CONF_C, TRANS_DDI_C, "Pipe C", false},
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};
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int selected = -1;
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for (int pass = 0; pass < 2 && selected < 0; pass++) {
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for (int i = 0; i < (int)(sizeof(candidates) / sizeof(candidates[0])); i++) {
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uint32_t conf = ReadReg(candidates[i].conf);
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uint32_t ddi = ReadReg(candidates[i].ddi);
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if (!(conf & PIPECONF_ENABLE)) continue;
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if (pass == 0 && !(ddi & TRANS_DDI_ENABLE)) continue;
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selected = i;
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break;
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}
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}
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if (selected < 0) selected = 1; // conservative legacy Pipe A fallback
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const auto& trans = candidates[selected];
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g_transTimingBase = trans.timing;
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g_transConfReg = trans.conf;
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g_transDdiReg = trans.ddi;
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g_connectorConnected = (ReadReg(trans.conf) & PIPECONF_ENABLE) != 0;
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uint32_t ddi = ReadReg(trans.ddi);
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if (g_gpuGen <= 7) {
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if (ReadReg(LVDS) & LVDS_PORT_ENABLE) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_LVDS;
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CopyText(g_connectorName, sizeof(g_connectorName), "LVDS-1");
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} else if (ReadReg(ADPA) & ADPA_DAC_ENABLE) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_VGA;
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CopyText(g_connectorName, sizeof(g_connectorName), "VGA-1");
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} else if ((ReadReg(DP_B) | ReadReg(DP_C) | ReadReg(DP_D)) & (1u << 31)) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_DP;
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CopyText(g_connectorName, sizeof(g_connectorName), "DP-1");
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} else {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_HDMI;
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CopyText(g_connectorName, sizeof(g_connectorName), "HDMI-1");
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}
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} else if (trans.edp) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_EDP;
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CopyText(g_connectorName, sizeof(g_connectorName), "eDP-1");
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} else {
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uint32_t mode = (ddi & TRANS_DDI_MODE_MASK) >> 24;
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uint32_t port = (ddi & TRANS_DDI_PORT_MASK) >> 27;
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const char* suffix = port == 0 ? "A" : port == 1 ? "B"
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: port == 2 ? "C" : port == 3 ? "D"
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: port == 8 ? "TC1" : port == 9 ? "TC2"
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: port == 10 ? "TC3" : port == 11 ? "TC4"
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: "unknown";
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if (mode == 0) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_HDMI;
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CopyText(g_connectorName, sizeof(g_connectorName), "HDMI-");
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} else if (mode == 1) {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_DVI;
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CopyText(g_connectorName, sizeof(g_connectorName), "DVI-");
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} else {
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g_connectorType = montauk::abi::DISPLAY_CONNECTOR_DP;
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CopyText(g_connectorName, sizeof(g_connectorName), "DP-");
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}
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uint64_t len = 0;
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while (len + 1 < sizeof(g_connectorName) && g_connectorName[len]) len++;
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CopyText(g_connectorName + len, sizeof(g_connectorName) - len, suffix);
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}
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KernelLogStream(OK, "IntelGPU") << "Active transcoder " << trans.name
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<< ", connector " << g_connectorName
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<< (g_connectorConnected ? " connected" : " disconnected");
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}
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static DisplayMode CaptureActiveMode() {
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DisplayMode mode = {};
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uint32_t htotal = ReadReg(g_transTimingBase + 0x00);
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uint32_t hsync = ReadReg(g_transTimingBase + 0x08);
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uint32_t vtotal = ReadReg(g_transTimingBase + 0x0C);
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uint32_t vsync = ReadReg(g_transTimingBase + 0x14);
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mode.hdisplay = (htotal & 0xFFFF) + 1;
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mode.htotal = ((htotal >> 16) & 0xFFFF) + 1;
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mode.hsyncStart = (hsync & 0xFFFF) + 1;
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mode.hsyncEnd = ((hsync >> 16) & 0xFFFF) + 1;
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mode.vdisplay = (vtotal & 0xFFFF) + 1;
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mode.vtotal = ((vtotal >> 16) & 0xFFFF) + 1;
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mode.vsyncStart = (vsync & 0xFFFF) + 1;
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mode.vsyncEnd = ((vsync >> 16) & 0xFFFF) + 1;
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return mode;
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}
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static void SelectCurrentMode() {
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DisplayMode active = CaptureActiveMode();
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if (active.hdisplay == 0 || active.hdisplay > 16384
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|| active.vdisplay == 0 || active.vdisplay > 16384) {
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active.hdisplay = (uint32_t)g_fbWidth;
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active.vdisplay = (uint32_t)g_fbHeight;
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}
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// Match the register totals against a detailed EDID timing to recover
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// the firmware-selected pixel clock exactly.
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for (int i = 0; i < g_modeCount; i++) {
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const auto& timing = g_modes[i].timing;
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if (timing.hdisplay == active.hdisplay && timing.vdisplay == active.vdisplay
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&& timing.htotal == active.htotal && timing.vtotal == active.vtotal
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&& timing.pixelClock != 0) {
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active.pixelClock = timing.pixelClock;
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active.hsyncPositive = timing.hsyncPositive;
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active.vsyncPositive = timing.vsyncPositive;
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g_currentMode = i;
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break;
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}
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}
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uint32_t refresh = ModeRefreshMilliHz(active);
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if (refresh == 0) refresh = 60000;
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if (g_currentMode < 0) g_currentMode = AddMode(active, refresh, 0);
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if (g_currentMode < 0 && g_modeCount == MaxDisplayModes) {
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// A pathological EDID can fill the catalogue before the firmware
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// mode is considered. The active mode is never optional: retain
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// it by replacing the final non-preferred catalogue entry.
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int replacement = MaxDisplayModes - 1;
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for (int i = MaxDisplayModes - 1; i >= 0; i--) {
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if (!(g_modes[i].flags & montauk::abi::DISPLAY_MODE_PREFERRED)) {
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replacement = i;
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break;
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}
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}
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g_modes[replacement].timing = active;
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g_modes[replacement].refreshMilliHz = refresh;
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g_modes[replacement].flags = 0;
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g_currentMode = replacement;
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}
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if (g_currentMode < 0) return;
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g_modes[g_currentMode].flags |= montauk::abi::DISPLAY_MODE_CURRENT
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| montauk::abi::DISPLAY_MODE_DRIVER_VALID;
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uint32_t activeClock = g_modes[g_currentMode].timing.pixelClock;
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for (int i = 0; i < g_modeCount; i++) {
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const auto& mode = g_modes[i].timing;
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if (mode.hdisplay == active.hdisplay && mode.vdisplay == active.vdisplay
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&& mode.pixelClock != 0 && activeClock != 0
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&& mode.pixelClock == activeClock) {
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g_modes[i].flags |= montauk::abi::DISPLAY_MODE_DRIVER_VALID;
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}
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}
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}
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static void DiscoverPwm() {
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g_pwmSupported = false;
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if (g_connectorType != montauk::abi::DISPLAY_CONNECTOR_EDP
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&& g_connectorType != montauk::abi::DISPLAY_CONNECTOR_LVDS)
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||||
return;
|
||||
|
||||
uint32_t pch = ReadReg(BLC_PWM_PCH_CTL2);
|
||||
if ((pch >> 16) != 0) {
|
||||
g_pwmCtlReg = BLC_PWM_PCH_CTL2;
|
||||
g_pwmSupported = true;
|
||||
} else {
|
||||
uint32_t cpu = ReadReg(BLC_PWM_CPU_CTL);
|
||||
if ((cpu >> 16) != 0) {
|
||||
g_pwmCtlReg = BLC_PWM_CPU_CTL;
|
||||
g_pwmSupported = true;
|
||||
}
|
||||
}
|
||||
KernelLogStream(INFO, "IntelGPU") << "Panel PWM "
|
||||
<< (g_pwmSupported ? "available" : "not exposed");
|
||||
}
|
||||
|
||||
static void InitializeDisplayManagement() {
|
||||
g_modeCount = 0;
|
||||
g_currentMode = -1;
|
||||
g_edidValid = false;
|
||||
CopyText(g_monitorName, sizeof(g_monitorName), "Unknown display");
|
||||
DiscoverActiveTranscoder();
|
||||
ParseEdid();
|
||||
SelectCurrentMode();
|
||||
DiscoverPwm();
|
||||
}
|
||||
|
||||
// =========================================================================
|
||||
// GTT Initialization
|
||||
// =========================================================================
|
||||
@@ -850,6 +1244,7 @@ namespace Drivers::Graphics::IntelGPU {
|
||||
KernelLogStream(ERROR, "IntelGPU") << "Failed to read display state";
|
||||
return false;
|
||||
}
|
||||
InitializeDisplayManagement();
|
||||
|
||||
if (!InitializeGtt()) {
|
||||
KernelLogStream(ERROR, "IntelGPU") << "Failed to initialize GTT";
|
||||
@@ -910,6 +1305,7 @@ namespace Drivers::Graphics::IntelGPU {
|
||||
KernelLogStream(ERROR, "IntelGPU") << "Failed to read display state";
|
||||
return;
|
||||
}
|
||||
InitializeDisplayManagement();
|
||||
|
||||
// Step 5: Initialize GTT
|
||||
if (!InitializeGtt()) {
|
||||
@@ -976,6 +1372,205 @@ namespace Drivers::Graphics::IntelGPU {
|
||||
return g_fbPitch;
|
||||
}
|
||||
|
||||
// =========================================================================
|
||||
// Display management public API
|
||||
// =========================================================================
|
||||
|
||||
static bool WaitTranscoderState(bool enabled) {
|
||||
for (int i = 0; i < 200000; i++) {
|
||||
bool state = (ReadReg(g_transConfReg) & PIPECONF_STATE) != 0;
|
||||
if (state == enabled) return true;
|
||||
asm volatile("pause");
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
struct TimingSnapshot {
|
||||
uint32_t htotal, hblank, hsync;
|
||||
uint32_t vtotal, vblank, vsync;
|
||||
};
|
||||
|
||||
static TimingSnapshot ReadTimingSnapshot() {
|
||||
return {
|
||||
ReadReg(g_transTimingBase + 0x00),
|
||||
ReadReg(g_transTimingBase + 0x04),
|
||||
ReadReg(g_transTimingBase + 0x08),
|
||||
ReadReg(g_transTimingBase + 0x0C),
|
||||
ReadReg(g_transTimingBase + 0x10),
|
||||
ReadReg(g_transTimingBase + 0x14),
|
||||
};
|
||||
}
|
||||
|
||||
static void WriteTimingSnapshot(const TimingSnapshot& timing) {
|
||||
WriteReg(g_transTimingBase + 0x00, timing.htotal);
|
||||
WriteReg(g_transTimingBase + 0x04, timing.hblank);
|
||||
WriteReg(g_transTimingBase + 0x08, timing.hsync);
|
||||
WriteReg(g_transTimingBase + 0x0C, timing.vtotal);
|
||||
WriteReg(g_transTimingBase + 0x10, timing.vblank);
|
||||
WriteReg(g_transTimingBase + 0x14, timing.vsync);
|
||||
}
|
||||
|
||||
static uint32_t PackTiming(uint32_t start, uint32_t end) {
|
||||
return ((end - 1) << 16) | (start - 1);
|
||||
}
|
||||
|
||||
static bool ApplyModeTiming(const DisplayMode& mode) {
|
||||
if (!g_connectorConnected || mode.hdisplay == 0 || mode.vdisplay == 0
|
||||
|| mode.htotal <= mode.hdisplay || mode.vtotal <= mode.vdisplay
|
||||
|| mode.hsyncStart < mode.hdisplay || mode.hsyncEnd <= mode.hsyncStart
|
||||
|| mode.hsyncEnd > mode.htotal || mode.vsyncStart < mode.vdisplay
|
||||
|| mode.vsyncEnd <= mode.vsyncStart || mode.vsyncEnd > mode.vtotal)
|
||||
return false;
|
||||
|
||||
TimingSnapshot oldTiming = ReadTimingSnapshot();
|
||||
uint32_t oldConf = ReadReg(g_transConfReg);
|
||||
uint32_t oldPlane = ReadReg(DSPACNTR);
|
||||
uint64_t oldSurface = (g_flipSupported && g_frontBuffer == 1)
|
||||
? g_buf1GttOffset
|
||||
: (g_flipSupported ? g_fbGttOffsetA : g_fbGttOffset);
|
||||
|
||||
// A timing-only modeset retains the firmware-trained DDI, PLL and link.
|
||||
// Disable fetch and the transcoder, program all timing registers as one
|
||||
// transaction, then restore them in the inverse order.
|
||||
if (oldPlane & DISP_ENABLE) {
|
||||
WriteReg(DSPACNTR, oldPlane & ~DISP_ENABLE);
|
||||
WriteReg(DSPASURF, (uint32_t)oldSurface);
|
||||
(void)ReadReg(DSPASURF);
|
||||
}
|
||||
WriteReg(g_transConfReg, oldConf & ~PIPECONF_ENABLE);
|
||||
if (!WaitTranscoderState(false)) {
|
||||
WriteReg(DSPACNTR, oldPlane);
|
||||
WriteReg(DSPASURF, (uint32_t)oldSurface);
|
||||
return false;
|
||||
}
|
||||
|
||||
TimingSnapshot next = {
|
||||
PackTiming(mode.hdisplay, mode.htotal),
|
||||
PackTiming(mode.hdisplay, mode.htotal),
|
||||
PackTiming(mode.hsyncStart, mode.hsyncEnd),
|
||||
PackTiming(mode.vdisplay, mode.vtotal),
|
||||
PackTiming(mode.vdisplay, mode.vtotal),
|
||||
PackTiming(mode.vsyncStart, mode.vsyncEnd),
|
||||
};
|
||||
WriteTimingSnapshot(next);
|
||||
WriteReg(g_transConfReg, oldConf | PIPECONF_ENABLE);
|
||||
if (!WaitTranscoderState(true)) {
|
||||
// Roll back while the transcoder is stopped. A failed timing must
|
||||
// never leave the panel black merely because userspace requested it.
|
||||
WriteReg(g_transConfReg, oldConf & ~PIPECONF_ENABLE);
|
||||
(void)WaitTranscoderState(false);
|
||||
WriteTimingSnapshot(oldTiming);
|
||||
WriteReg(g_transConfReg, oldConf);
|
||||
(void)WaitTranscoderState((oldConf & PIPECONF_ENABLE) != 0);
|
||||
WriteReg(DSPACNTR, oldPlane);
|
||||
WriteReg(DSPASURF, (uint32_t)oldSurface);
|
||||
(void)ReadReg(DSPASURF);
|
||||
return false;
|
||||
}
|
||||
|
||||
WriteReg(DSPACNTR, oldPlane);
|
||||
WriteReg(DSPASURF, (uint32_t)oldSurface);
|
||||
(void)ReadReg(DSPASURF);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool GetDisplayInfo(montauk::abi::DisplayInfo* out) {
|
||||
if (!out) return false;
|
||||
memset(out, 0, sizeof(*out));
|
||||
out->brightness = -1;
|
||||
out->currentMode = -1;
|
||||
if (!g_initialized) return false;
|
||||
|
||||
out->capabilities = montauk::abi::DISPLAY_CAP_MODESET;
|
||||
if (g_edidValid) out->capabilities |= montauk::abi::DISPLAY_CAP_EDID;
|
||||
if (g_pwmSupported) out->capabilities |= montauk::abi::DISPLAY_CAP_BRIGHTNESS;
|
||||
if (g_flipSupported) out->capabilities |= montauk::abi::DISPLAY_CAP_PAGE_FLIP;
|
||||
if (g_vblankIrqReady) out->capabilities |= montauk::abi::DISPLAY_CAP_VBLANK_IRQ;
|
||||
for (int i = 0; i < g_modeCount; i++) {
|
||||
if (i != g_currentMode
|
||||
&& (g_modes[i].flags & montauk::abi::DISPLAY_MODE_DRIVER_VALID)) {
|
||||
out->capabilities |= montauk::abi::DISPLAY_CAP_SAFE_SWITCH;
|
||||
break;
|
||||
}
|
||||
}
|
||||
out->modeCount = (uint32_t)g_modeCount;
|
||||
out->currentMode = g_currentMode;
|
||||
out->brightness = Brightness(-1);
|
||||
out->deviceId = g_gpuInfo.deviceId;
|
||||
out->generation = g_gpuInfo.gen;
|
||||
out->connectorType = g_connectorType;
|
||||
out->connected = g_connectorConnected ? 1 : 0;
|
||||
CopyText(out->gpuName, sizeof(out->gpuName),
|
||||
g_gpuInfo.name ? g_gpuInfo.name : "Intel GPU");
|
||||
CopyText(out->connectorName, sizeof(out->connectorName), g_connectorName);
|
||||
CopyText(out->monitorName, sizeof(out->monitorName), g_monitorName);
|
||||
return true;
|
||||
}
|
||||
|
||||
int GetDisplayModes(montauk::abi::DisplayModeInfo* out, int maxCount) {
|
||||
if (!g_initialized || maxCount < 0) return -1;
|
||||
int count = g_modeCount < maxCount ? g_modeCount : maxCount;
|
||||
if (count > 0 && !out) return -1;
|
||||
for (int i = 0; i < count; i++) {
|
||||
out[i].width = g_modes[i].timing.hdisplay;
|
||||
out[i].height = g_modes[i].timing.vdisplay;
|
||||
out[i].refreshMilliHz = g_modes[i].refreshMilliHz;
|
||||
out[i].pixelClockKHz = g_modes[i].timing.pixelClock;
|
||||
out[i].flags = g_modes[i].flags;
|
||||
out[i]._pad = 0;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
int SetDisplayMode(int modeIndex) {
|
||||
if (!g_initialized || modeIndex < 0 || modeIndex >= g_modeCount) return -1;
|
||||
if (g_currentMode < 0 || g_currentMode >= g_modeCount) return -1;
|
||||
if (!(g_modes[modeIndex].flags & montauk::abi::DISPLAY_MODE_DRIVER_VALID))
|
||||
return -2;
|
||||
if (modeIndex == g_currentMode) return modeIndex;
|
||||
|
||||
// Link rate and framebuffer geometry remain fixed. Only timings with
|
||||
// the same active area and pixel clock are safe without retraining the
|
||||
// firmware-established HDMI/DP/eDP link.
|
||||
const DisplayMode& current = g_modes[g_currentMode].timing;
|
||||
const DisplayMode& requested = g_modes[modeIndex].timing;
|
||||
if (requested.hdisplay != current.hdisplay
|
||||
|| requested.vdisplay != current.vdisplay
|
||||
|| requested.pixelClock == 0
|
||||
|| requested.pixelClock != current.pixelClock)
|
||||
return -2;
|
||||
|
||||
if (!ApplyModeTiming(requested)) {
|
||||
KernelLogStream(ERROR, "IntelGPU") << "Modeset transaction failed; previous mode restored";
|
||||
return -3;
|
||||
}
|
||||
|
||||
g_modes[g_currentMode].flags &= ~montauk::abi::DISPLAY_MODE_CURRENT;
|
||||
g_currentMode = modeIndex;
|
||||
g_modes[g_currentMode].flags |= montauk::abi::DISPLAY_MODE_CURRENT;
|
||||
KernelLogStream(OK, "IntelGPU") << "Mode set to " << base::dec
|
||||
<< (uint64_t)requested.hdisplay << "x" << (uint64_t)requested.vdisplay
|
||||
<< " @ " << (uint64_t)(g_modes[modeIndex].refreshMilliHz / 1000) << "Hz";
|
||||
return modeIndex;
|
||||
}
|
||||
|
||||
int Brightness(int percent) {
|
||||
if (!g_initialized || !g_pwmSupported) return -1;
|
||||
uint32_t value = ReadReg(g_pwmCtlReg);
|
||||
uint32_t maximum = value >> 16;
|
||||
if (maximum == 0) return -1;
|
||||
if (percent < 0) {
|
||||
uint32_t duty = value & 0xFFFF;
|
||||
if (duty > maximum) duty = maximum;
|
||||
return (int)(((uint64_t)duty * 100 + maximum / 2) / maximum);
|
||||
}
|
||||
if (percent > 100) percent = 100;
|
||||
uint32_t duty = (uint32_t)(((uint64_t)maximum * (uint32_t)percent + 50) / 100);
|
||||
WriteReg(g_pwmCtlReg, (value & 0xFFFF0000u) | duty);
|
||||
(void)ReadReg(g_pwmCtlReg);
|
||||
return Brightness(-1);
|
||||
}
|
||||
|
||||
// =========================================================================
|
||||
// Page flip public API
|
||||
// =========================================================================
|
||||
|
||||
Reference in new issue
Block a user