feat: further kernel power and power optimizations
This commit is contained in:
@@ -0,0 +1,514 @@
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/*
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* CpuIdle.cpp
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* ACPI-guided CPU idle-state selection
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* Copyright (c) 2026 Daniel Hammer
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*/
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#include "CpuIdle.hpp"
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#include <ACPI/FADT.hpp>
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#include <ACPI/AML/AmlInterpreter.hpp>
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#include <Hal/Cpu.hpp>
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#include <Io/IoPort.hpp>
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#include <Terminal/Terminal.hpp>
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#include <CppLib/Stream.hpp>
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using namespace Kt;
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namespace Hal {
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namespace CpuIdle {
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enum class IdleEntryKind : uint8_t {
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FixedHardware,
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IoPort,
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};
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struct IdleState {
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bool Valid = false;
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uint8_t CType = 0;
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uint32_t LatencyUs = 0;
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uint32_t PowerMw = 0;
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IdleEntryKind EntryKind = IdleEntryKind::FixedHardware;
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uint16_t IoPort = 0;
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uint8_t WidthBits = 0;
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};
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static constexpr int MaxIdleStates = 8;
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static constexpr uint8_t GAS_SYSTEM_IO = 0x01;
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static constexpr uint8_t GAS_FIXED_HARDWARE = 0x7F;
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static constexpr uint32_t ResidencyLatencyRatio = 8;
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static constexpr uint32_t IoStateMinPredictedMs = 20;
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static constexpr uint16_t LegacyC2MaxLatencyUs = 100;
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static IdleState g_idleStates[MaxIdleStates]{};
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static int g_idleStateCount = 0;
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static volatile uint64_t g_fallbackMonitor = 0;
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static uint64_t ReadLe64(const uint8_t* data) {
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uint64_t value = 0;
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for (int i = 0; i < 8; i++) {
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value |= (uint64_t)data[i] << (i * 8);
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}
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return value;
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}
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static bool IsName(const char* actual, const char* expected) {
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for (int i = 0; i < 4; i++) {
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if (actual[i] != expected[i]) {
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return false;
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}
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}
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return true;
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}
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static uint32_t DecodePkgLength(const uint8_t* aml, uint32_t length, uint32_t& pos) {
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if (pos >= length) return 0;
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uint8_t lead = aml[pos];
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uint32_t byteCount = (lead >> 6) & 0x03;
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if (byteCount == 0) {
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pos++;
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return lead & 0x3F;
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}
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uint32_t value = lead & 0x0F;
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pos++;
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for (uint32_t i = 0; i < byteCount && pos < length; i++) {
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value |= (uint32_t)aml[pos++] << (4 + 8 * i);
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}
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return value;
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}
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static bool DecodeInteger(const uint8_t* aml, uint32_t length, uint32_t& pos, uint64_t& value) {
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if (pos >= length) return false;
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uint8_t op = aml[pos];
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switch (op) {
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case AML::ZeroOp:
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value = 0;
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pos++;
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return true;
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case AML::OneOp:
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value = 1;
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pos++;
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return true;
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case AML::BytePrefix:
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if (pos + 1 >= length) return false;
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value = aml[pos + 1];
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pos += 2;
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return true;
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case AML::WordPrefix:
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if (pos + 2 >= length) return false;
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value = (uint16_t)aml[pos + 1] | ((uint16_t)aml[pos + 2] << 8);
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pos += 3;
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return true;
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case AML::DWordPrefix:
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if (pos + 4 >= length) return false;
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value = (uint32_t)aml[pos + 1]
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| ((uint32_t)aml[pos + 2] << 8)
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| ((uint32_t)aml[pos + 3] << 16)
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| ((uint32_t)aml[pos + 4] << 24);
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pos += 5;
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return true;
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case AML::QWordPrefix:
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if (pos + 8 >= length) return false;
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value = ReadLe64(&aml[pos + 1]);
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pos += 9;
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return true;
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default:
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return false;
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}
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}
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static bool DecodeBufferObject(const uint8_t* aml, uint32_t length, uint32_t& pos,
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const uint8_t*& data, uint32_t& dataLength) {
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if (pos >= length || aml[pos] != AML::BufferOp) return false;
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pos++;
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uint32_t pkgStart = pos;
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uint32_t pkgLen = DecodePkgLength(aml, length, pos);
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uint32_t end = pkgStart + pkgLen;
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if (end > length) end = length;
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uint64_t declaredLength = 0;
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if (!DecodeInteger(aml, end, pos, declaredLength)) {
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return false;
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}
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data = &aml[pos];
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dataLength = (uint32_t)(end - pos);
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if (declaredLength < dataLength) {
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dataLength = (uint32_t)declaredLength;
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}
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pos = end;
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return true;
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}
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static bool DecodePackageObject(const uint8_t* aml, uint32_t length, uint32_t& pos,
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const uint8_t*& data, uint32_t& dataLength) {
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if (pos >= length) return false;
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if (aml[pos] != AML::PackageOp && aml[pos] != AML::VarPackageOp) return false;
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pos++;
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uint32_t pkgStart = pos;
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uint32_t pkgLen = DecodePkgLength(aml, length, pos);
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uint32_t end = pkgStart + pkgLen;
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if (end > length) end = length;
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data = &aml[pos];
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dataLength = (uint32_t)(end - pos);
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pos = end;
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return true;
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}
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static const char* EntryKindName(const IdleState& state) {
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return (state.EntryKind == IdleEntryKind::IoPort) ? "ioport" : "fixed";
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}
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static bool ParseGas(const uint8_t* buffer, uint32_t length, IdleState& state) {
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if (length < 12) {
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return false;
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}
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uint8_t addressSpace = buffer[0];
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uint8_t bitWidth = buffer[1];
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uint8_t accessSize = buffer[3];
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uint64_t address = ReadLe64(&buffer[4]);
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if (addressSpace == GAS_FIXED_HARDWARE) {
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state.EntryKind = IdleEntryKind::FixedHardware;
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return true;
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}
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if (addressSpace != GAS_SYSTEM_IO || address == 0 || address > 0xFFFF) {
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return false;
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}
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uint8_t widthBits = bitWidth;
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if (widthBits == 0) {
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switch (accessSize) {
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case 1: widthBits = 8; break;
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case 2: widthBits = 16; break;
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case 3: widthBits = 32; break;
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default: widthBits = 8; break;
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}
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}
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if (widthBits != 8 && widthBits != 16 && widthBits != 32) {
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return false;
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}
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state.EntryKind = IdleEntryKind::IoPort;
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state.IoPort = (uint16_t)address;
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state.WidthBits = widthBits;
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return true;
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}
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static bool ParseIdleStatePackage(const uint8_t* aml, uint32_t length, IdleState& state) {
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if (length < 2) return false;
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uint32_t pos = 1; // skip package element count byte
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const uint8_t* regData = nullptr;
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uint32_t regLength = 0;
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uint64_t type = 0;
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uint64_t latency = 0;
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uint64_t power = 0;
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if (!DecodeBufferObject(aml, length, pos, regData, regLength)) {
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return false;
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}
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if (!DecodeInteger(aml, length, pos, type)) {
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return false;
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}
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if (!DecodeInteger(aml, length, pos, latency)) {
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return false;
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}
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if (!DecodeInteger(aml, length, pos, power)) {
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return false;
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}
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state = {};
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state.CType = (uint8_t)type;
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state.LatencyUs = (uint32_t)latency;
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state.PowerMw = (uint32_t)power;
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if (!ParseGas(regData, regLength, state)) {
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return false;
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}
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state.Valid = true;
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return true;
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}
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static bool ParseCstObject(const char* path, const AML::Object& obj) {
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if (obj.Type != AML::ObjectType::Package || obj.Buffer.Length < 2) {
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return false;
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}
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uint32_t pos = 1; // package element count byte
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uint64_t declaredStateCount = 0;
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if (!DecodeInteger(obj.Buffer.Data, obj.Buffer.Length, pos, declaredStateCount)) {
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return false;
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}
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int parsedCount = 0;
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for (uint64_t i = 0; i < declaredStateCount && parsedCount < MaxIdleStates; i++) {
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const uint8_t* nestedData = nullptr;
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uint32_t nestedLength = 0;
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if (!DecodePackageObject(obj.Buffer.Data, obj.Buffer.Length, pos, nestedData, nestedLength)) {
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break;
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}
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IdleState state{};
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if (!ParseIdleStatePackage(nestedData, nestedLength, state)) {
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continue;
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}
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g_idleStates[parsedCount++] = state;
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}
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if (parsedCount == 0) {
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return false;
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}
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g_idleStateCount = parsedCount;
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KernelLogStream(OK, "CpuIdle") << "Loaded " << base::dec
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<< (uint64_t)g_idleStateCount << " ACPI idle state(s) from " << path;
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for (int i = 0; i < g_idleStateCount; i++) {
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const auto& state = g_idleStates[i];
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KernelLogStream(INFO, "CpuIdle") << "C" << base::dec << (uint64_t)state.CType
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<< " latency=" << (uint64_t)state.LatencyUs << "us"
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<< " power=" << (uint64_t)state.PowerMw << "mW"
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<< " entry=" << EntryKindName(state);
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}
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return true;
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}
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static bool LoadLegacyPblkIdleStates(const FADT::ParsedFADT& fadt) {
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if (!fadt.Valid ||
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fadt.WorstC2Latency == 0 ||
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fadt.WorstC2Latency > LegacyC2MaxLatencyUs) {
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return false;
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}
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auto& interp = AML::GetInterpreter();
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if (!interp.IsInitialized()) {
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return false;
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}
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auto& ns = interp.GetNamespace();
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char path[256];
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for (int32_t nodeIndex = 0; nodeIndex < ns.NodeCount(); nodeIndex++) {
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auto* node = ns.GetNode(nodeIndex);
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if (node == nullptr || node->Obj.Type != AML::ObjectType::Processor) {
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continue;
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}
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uint32_t pblk = node->Obj.Processor.PblkAddr;
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uint8_t pblkLen = node->Obj.Processor.PblkLen;
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if (pblk == 0 || pblk > 0xFFFF || pblkLen < 5) {
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continue;
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}
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IdleState c1{};
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c1.Valid = true;
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c1.CType = 1;
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c1.LatencyUs = 1;
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c1.EntryKind = IdleEntryKind::FixedHardware;
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IdleState c2{};
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c2.Valid = true;
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c2.CType = 2;
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c2.LatencyUs = fadt.WorstC2Latency;
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c2.EntryKind = IdleEntryKind::IoPort;
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c2.IoPort = (uint16_t)(pblk + 4); // ACPI legacy P_LVL2 register
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c2.WidthBits = 8;
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g_idleStates[0] = c1;
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g_idleStates[1] = c2;
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g_idleStateCount = 2;
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ns.GetNodePath(nodeIndex, path, sizeof(path));
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KernelLogStream(OK, "CpuIdle") << "Using legacy ACPI P_BLK C2 idle state from "
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<< path << " latency=" << base::dec << (uint64_t)c2.LatencyUs
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<< "us port=" << base::hex << (uint64_t)c2.IoPort;
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return true;
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}
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return false;
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}
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static const IdleState* SelectIdleState(uint32_t predictedIdleMs, bool hasMwait) {
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uint64_t predictedIdleUs = (uint64_t)predictedIdleMs * 1000;
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const IdleState* best = nullptr;
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for (int i = 0; i < g_idleStateCount; i++) {
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const auto& state = g_idleStates[i];
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if (!state.Valid) continue;
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// Keep the first implementation conservative: skip ACPI I/O
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// states deeper than C2 until cache/bus-master coordination is
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// implemented.
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if (state.EntryKind == IdleEntryKind::IoPort && state.CType > 2) {
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continue;
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}
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if (state.EntryKind == IdleEntryKind::IoPort &&
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predictedIdleMs < IoStateMinPredictedMs) {
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continue;
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}
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if (state.CType > 1 && state.LatencyUs != 0 &&
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predictedIdleUs < (uint64_t)state.LatencyUs * ResidencyLatencyRatio) {
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continue;
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}
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if (state.EntryKind == IdleEntryKind::FixedHardware && !hasMwait &&
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state.CType > 1) {
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continue;
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}
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if (best == nullptr || state.CType >= best->CType) {
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best = &state;
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}
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}
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return best;
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}
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static void FallbackWait(bool hasMwait, volatile uint64_t* monitorAddr) {
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volatile uint64_t* addr = (monitorAddr != nullptr) ? monitorAddr : &g_fallbackMonitor;
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if (hasMwait) {
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Hal::IdleWait(addr);
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} else {
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asm volatile("hlt");
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}
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}
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static void FallbackWaitWithInterruptsDisabled(bool hasMwait,
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volatile uint64_t* monitorAddr) {
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volatile uint64_t* addr = (monitorAddr != nullptr) ? monitorAddr : &g_fallbackMonitor;
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if (hasMwait) {
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Hal::IdleWaitWithInterruptsDisabled(addr);
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} else {
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Hal::HaltWithInterruptsDisabled();
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}
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}
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static void EnterIoIdleWithInterruptsDisabled(const IdleState& state) {
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switch (state.WidthBits) {
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case 16: {
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uint16_t value;
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asm volatile("sti\n\tinw %w1, %w0\n\tcli"
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: "=a"(value) : "Nd"(state.IoPort) : "memory");
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break;
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}
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case 32: {
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uint32_t value;
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asm volatile("sti\n\tinl %w1, %0\n\tcli"
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: "=a"(value) : "Nd"(state.IoPort) : "memory");
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break;
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}
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default: {
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uint8_t value;
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asm volatile("sti\n\tinb %w1, %b0\n\tcli"
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: "=a"(value) : "Nd"(state.IoPort) : "memory");
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break;
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}
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}
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}
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void Initialize(ACPI::CommonSDTHeader* xsdt) {
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g_idleStateCount = 0;
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for (int i = 0; i < MaxIdleStates; i++) {
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g_idleStates[i] = {};
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}
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FADT::ParsedFADT fadt{};
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bool fadtReady = xsdt != nullptr && FADT::Parse(xsdt, fadt) && fadt.Valid;
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if (fadtReady && fadt.SMI_CommandPort != 0 && fadt.CStateControl != 0) {
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Io::Out8(fadt.CStateControl, (uint16_t)fadt.SMI_CommandPort);
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KernelLogStream(INFO, "CpuIdle") << "Advertised ACPI _CST support";
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}
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auto& interp = AML::GetInterpreter();
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if (!interp.IsInitialized()) {
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KernelLogStream(INFO, "CpuIdle") << "AML interpreter not ready - using MWAIT/HLT";
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return;
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}
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auto& ns = interp.GetNamespace();
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char path[256];
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for (int32_t nodeIndex = 0; nodeIndex < ns.NodeCount(); nodeIndex++) {
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auto* node = ns.GetNode(nodeIndex);
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if (node == nullptr) continue;
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if (!IsName(node->Name, "_CST")) continue;
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ns.GetNodePath(nodeIndex, path, sizeof(path));
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AML::Object obj{};
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if (!interp.EvaluateObject(path, obj)) {
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continue;
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}
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if (ParseCstObject(path, obj)) {
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return;
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}
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}
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if (fadtReady && LoadLegacyPblkIdleStates(fadt)) {
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return;
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}
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KernelLogStream(INFO, "CpuIdle")
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<< "ACPI _CST unavailable or unsupported - using safe MWAIT/HLT idle fallback";
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}
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void Wait(uint32_t predictedIdleMs, bool hasMwait, volatile uint64_t* monitorAddr) {
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const IdleState* state = SelectIdleState(predictedIdleMs, hasMwait);
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if (state == nullptr) {
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FallbackWait(hasMwait, monitorAddr);
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return;
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}
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if (state->EntryKind == IdleEntryKind::IoPort) {
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switch (state->WidthBits) {
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case 16:
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(void)Io::In16(state->IoPort);
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return;
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case 32:
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(void)Io::In32(state->IoPort);
|
||||
return;
|
||||
default:
|
||||
(void)Io::In8(state->IoPort);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
FallbackWait(hasMwait, monitorAddr);
|
||||
}
|
||||
|
||||
void WaitWithInterruptsDisabled(uint32_t predictedIdleMs, bool hasMwait,
|
||||
volatile uint64_t* monitorAddr) {
|
||||
const IdleState* state = SelectIdleState(predictedIdleMs, hasMwait);
|
||||
if (state != nullptr && state->EntryKind == IdleEntryKind::IoPort) {
|
||||
EnterIoIdleWithInterruptsDisabled(*state);
|
||||
return;
|
||||
}
|
||||
|
||||
FallbackWaitWithInterruptsDisabled(hasMwait, monitorAddr);
|
||||
}
|
||||
|
||||
void WaitShallowWithInterruptsDisabled(bool hasMwait, volatile uint64_t* monitorAddr) {
|
||||
FallbackWaitWithInterruptsDisabled(hasMwait, monitorAddr);
|
||||
}
|
||||
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* CpuIdle.hpp
|
||||
* ACPI-guided CPU idle-state selection
|
||||
* Copyright (c) 2026 Daniel Hammer
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include <ACPI/ACPI.hpp>
|
||||
|
||||
namespace Hal {
|
||||
namespace CpuIdle {
|
||||
|
||||
// Initialize ACPI idle-state policy from the AML namespace and FADT.
|
||||
void Initialize(ACPI::CommonSDTHeader* xsdt);
|
||||
|
||||
// Enter an idle state chosen for the predicted idle duration.
|
||||
// Falls back to MWAIT/HLT when ACPI data is unavailable.
|
||||
void Wait(uint32_t predictedIdleMs, bool hasMwait,
|
||||
volatile uint64_t* monitorAddr = nullptr);
|
||||
|
||||
// Same as Wait(), but called with interrupts disabled and returns with
|
||||
// interrupts disabled. Used by tickless idle paths that need atomic
|
||||
// STI+HLT/MWAIT semantics.
|
||||
void WaitWithInterruptsDisabled(uint32_t predictedIdleMs, bool hasMwait,
|
||||
volatile uint64_t* monitorAddr = nullptr);
|
||||
|
||||
// Shallow atomic idle for latency-sensitive interactive bursts.
|
||||
void WaitShallowWithInterruptsDisabled(bool hasMwait,
|
||||
volatile uint64_t* monitorAddr = nullptr);
|
||||
|
||||
};
|
||||
};
|
||||
@@ -78,6 +78,9 @@ namespace Hal {
|
||||
result.PM1EventLength = fadt->PM1EventLength;
|
||||
result.GPE0Length = fadt->GPE0Length;
|
||||
result.GPE1Length = fadt->GPE1Length;
|
||||
result.CStateControl = fadt->CStateControl;
|
||||
result.WorstC2Latency = fadt->WorstC2Latency;
|
||||
result.WorstC3Latency = fadt->WorstC3Latency;
|
||||
result.AcpiEnable = fadt->AcpiEnable;
|
||||
result.AcpiDisable = fadt->AcpiDisable;
|
||||
result.Flags = fadt->Flags;
|
||||
|
||||
@@ -85,6 +85,9 @@ namespace Hal {
|
||||
uint8_t PM1EventLength;
|
||||
uint8_t GPE0Length;
|
||||
uint8_t GPE1Length;
|
||||
uint8_t CStateControl;
|
||||
uint16_t WorstC2Latency;
|
||||
uint16_t WorstC3Latency;
|
||||
uint8_t AcpiEnable;
|
||||
uint8_t AcpiDisable;
|
||||
uint32_t Flags;
|
||||
|
||||
Reference in New Issue
Block a user